Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 17 of 17 for “"Clock and Data Recovery"”.
-
Circuit architectures for high speed CMOS clock and data recovery circuits
… process technologies continue to scale and the demand for ubiquitous computing devices continues to grow with paradigms such as the internet of things (IOT), the availability of low-cost, low-power, high-speed and robust communication interfaces between these devices will be a major …
-
A 2.5 Gb/s SONET clock and data recovery macro cell
… of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
-
Design of a clock and data recovery circuit in 65 nm technology
… fabrication technology develops, the demand for higher transmission data rates constantly increases; thus there is an urgent need for a power-efficient, robust and broad bandwidth chip-to-chip communication method. A lot of work has been done to address this issue as researchers strive …
-
Modelling and applications of MOS varactors for high-speed CMOS clock and data recovery
The high-speed clock and data recovery (CDR) circuit is a key building block of modern communication systems with applications spanning a wide range from wireline long-haul networks to chip-to-chip and backplane communications. In this dissertation, our focus is on the modelling, design and …
-
Design and modelling of clock and data recovery integrated circuit in 130 nm CMOS technology for 10 Gb/s serial data communications
This thesis describes the design and implementation of a fully monolithic 10 Gb/s phase and frequency-locked loop based clock and data recovery (PFLL-CDR) integrated circuit, as well as the Verilog-A modeling of an asynchronous serial link based chip to chip communication system incorporating the …
-
5GHz CMOS resonant clock buffer with quadrature generation for fiber optic applications
Clock buffers constitute a major source of power dissipation in VLSI circuits. In CMOS the load is primarily capacitive and hence an inductive shunt can reduce real power needs. This almost-adiabatic topology is referred to as a resonant buffer. Two resonant buffers can be actively controlled by …
-
Energy-efficient wireline transceivers
… wireline transceivers are highly demanded by many applications in high performance computation and communication systems. Apart from transferring a wide range of data rates to satisfy the interconnect bandwidth requirement, the transceivers have very tight power budget and are …
-
Low-power and energy-efficient wireline receivers
The exponential growth of data processing, ranging from edge devices to cloud computing, requires low-power and energy-efficient wireline data communication. This dissertation proposes innovative ways to accomplish such communication focusing on the receiver side. The first half of the dissertation …
-
Investigations of sub-systems for dynamic wavelength-routed optical networks
… describes an investigation of technologies and sub-systems required for physical layer implementation of a range of dynamic wavelength-routed optical networks with a specific focus on acknowledged optical-burst-switching (OBS) architectures where burst lengths are expected to be in the …
-
A new programmable low noise all digital phase-locked loop architecture
… loops (PLL) implemented within each system and often within each integrated circuit (IC). In fact, most PLL's are implemented monolithically within ICs without any or with very few external components. Additionally, most are implemented as Analog PLL's utilizing only a digital phase …
-
Architectural & circuit level techniques to improve energy efficiency of high speed serial links
High performance computing and communication are two key aspects of all information processing systems. With aggressive scaling of silicon technology enabling integration of a large number of transistors in a small area, managing power and thermal reliability has become very challenging. While …
-
CMOS Receiver Design for Optical Communications over the Data-Rate of 20 Gb/s
Circuits to extend operation data-rate of a optical receiver is investigated in the dissertation. A new input-stage topology for a transimpedance amplifier (TIA) is designed to achieve 50% higher data-rate is presented, and a new architecture for clock recovery is proposed for 50% higher clock …
-
Design of energy-efficient high-speed wireline transceiver
… The power problem permeates both computing and communication systems alike. Especially in the era of Big Data, continuously growing demand for higher communication bandwidth is driving the need for energy-efficient high-speed I/O serial links. However, the rate at which the energy efficiency …
-
Systems and circuits for broadband contactless and wireline transceivers
… have witnessed significant growth in global data traffic, primarily driven by the exponential increase in both the number of users and the amount of data processed by various applications. This has motivated the development of cost- and energy-efficient high-speed interconnects capable of …
-
Design and Implementation of Low Jitter Clock Generators in Communication and Aerospace System
The high demands on data processing and bandwidth in wireless/wireline communication and aerospace systems have been pushing forward circuit design techniques to their limitations to obtain maximum performances with respect to high operating frequency, low noise, small area, and low power …
-
Design of energy efficient high speed I/O interfaces
The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.