Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
Results
Showing 1 to 1 of 1 for “"Clock Network Buffer Sizing"”.
-
Development of an Accurate Clock Delay Model with Application in Clock Network Buffer Sizing
Clock network synthesis is an important stage of the Integrated Circuit (IC) design cycle. The performance of the IC highly depends on the clock network synthesis which makes this stage critical where accuracy is very important. In this thesis, a new delay model is proposed for clock networks that …