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Showing 1 to 1 of 1 for “"Circuitos de memória CMOS"”.

  1. Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process

    Since analog circuit designs in CMOS nanometer (< 90 nm) nodes can be substantially affected by manufacturing process variations, circuit performance becomes more challenging to achieve efficient solutions by using analytical models. Extensive simulations are thus commonly required to provide a …

    brazil-uerj Repository record for Study and development of low power consumption SRAMs on 28 nm FD-SOI CMOS process (opens in a new tab)