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Showing 1 to 5 of 5 for “"Circuit aging"”.

  1. A Study on Unintentional and Intentional Sources of Variability in Nanometer Scale Digital Circuits

    … in digital very large scale integrated (VLSI) circuits. Today's integrated circuits, which implement digital systems with billions of transistors in about a square centimeter, are tremendously susceptible to inadvertent errors, and circuit modifications required to ensure error resilience incur …

    umn Repository record for A Study on Unintentional and Intentional Sources of Variability in Nanometer Scale Digital Circuits (opens in a new tab)

  2. A Systematic Approach to Design an Efficient Physical Unclonable Function

    … in the logic and interconnect inside integrated circuits (ICs). An efficient PUF should generate a key that varies randomly from one chip to another. At the same time, it should reliably reproduce a key from a chip every time the key is requested from that chip. Moreover, a PUF should be robust …

    vt Repository record for A Systematic Approach to Design an Efficient Physical Unclonable Function (opens in a new tab)

  3. Changing edges in graphical model algorithms

    … in structures, such as the nodes in decoding circuits, agents in small-world networks, and neurons in our brains. These structures are often not static and can change over time, resulting in removal of edges, extra nodes, or changes in weights of the links in the graphs. For example, wires in …

    uiuc Repository record for Changing edges in graphical model algorithms (opens in a new tab)

  4. Comprehensive variation-aware aging simulator for logic timing and SRAM stability

    … research developed a framework which analyzes circuit-level reliability and evaluates the lifetimes of complex systems like state-of-art microprocessors. The novelty of the proposed work lies on its statistical timing analyzer and the ability to handle the combined effect of a variety of …

    gatech Repository record for Comprehensive variation-aware aging simulator for logic timing and SRAM stability (opens in a new tab)

  5. Neural ordinary differential equation models for circuits

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-15 without embargo terms

    uiuc Repository record for Neural ordinary differential equation models for circuits (opens in a new tab)