Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 15 of 15 for “"Chip Multiprocessors"”.
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Thread Scheduling For Chip Multiprocessors
Large, high frequency single-core chip designs are increasingly being replaced with larger chip multiprocessor (CMP) designs that tradeoff frequency for greater numbers of cores. Power has become a first-order design constraint, leading to designs optimized for computing efficiency, defined as the …
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Proximity coherence for chip-multiprocessors
… implement the most efficient solution for chip-multiprocessors, placing limits on the performance of these complex systems. In an era of increasingly power limited silicon design, efficiency is now a primary concern that motivates designers to look again at the challenge of cache coherence. …
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Chip Multiprocessors With Speculative Multithreading: Design for Performance and Energy Efficiency
… In fact, for the same average power in both chips, the SM CMP is 1.13 times faster than the 6-issue superscalar on average.
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An evaluation framework for massively parallel accelerator processors
… framework for Rigel, a 1024-core single-chip accelerator architecture designed for high throughput on visual computing and scientific workloads. I present an integrated evaluation framework for investigating co-designed architecture, compilers, programming models, and RTL implementation …
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AXCIS : rapid processor architectural exploration using canonical instruction segments
… are becoming more popular with the emergence of chip multiprocessors (CMP). For 24 SPEC CPU2000 benchmarks and all simulated configurations, AXCIS achieves an average IPC error of 2.6% and is over four orders of magnitude faster than conventional detailed simulation.
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Latency reduction techniques in chip multiprocessor cache systems
Single-chip multiprocessors (CMPs) solve several bottlenecks facing chip designers today. Compared to traditional superscalars, CMPs deliver higher performance at lower power for thread-parallel workloads. In this thesis, we consider tiled CMPs, a class of CMPs where each tile contains a slice of …
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Hardware-level fine-grained thread migration
… maximum performance. Massive-scale single-chip multiprocessors dramatically alter this picture. On-chip data transfer latencies-even across a 100+-core chip-rarely exceed tens of cycles, making the potential cost of thread migration as low as executing several instructions. At the same …
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Directoryless shared memory architecture using thread migration and remote access
Chip multiprocessors (CMPs) have become mainstream in recent years, and, for scalability reasons, high-core-count designs tend towards tiled CMPs with physically distributed caches. In order to support shared memory, current many-core CMPs maintain cache coherence using distributed directory …
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Fine-grained Adaptivity for Dynamic On-chip Networks
A key challenge of building chip multiprocessors (CMPs) is providing an efficient communication infrastructure for their increasing communication demands. Networks-on-Chip (NoCs) offer a scalable, high-bandwidth, low-latency solution to this problem, but unfortunately incur significant area and …
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Silicon Photonics for High-Performance Interconnection Networks
… computational parallelism associated with chip multiprocessors, memory systems, high-performance computing systems, and data centers. Sustaining these parallelism growths introduces unique challenges for on- and off-chip communications, shifting the focus toward novel and fundamentally …
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Performance and Memory Space Optimizations for Embedded Systems
… price (limited hardware). Embedded computers use chip multiprocessors (CMPs) to meet these expectations. However, one of the major problems is lack of efficient software support for CMPs; in particular, automated code parallelizers are needed.</p> <p>The aim of this study is to explore various …
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Design and analysis of spatially-partitioned shared caches
Data movement is a growing problem in modern chip-multiprocessors (CMPs). Processors spend the majority of their time, energy, and area moving data, not processing it. For example, a single main memory access takes hundreds of cycles and costs the energy of a thousand floating-point operations. …
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Implementation of a Hardware-Optimized MPI Library for the SCMP Multiprocessor
… designs. One potential solution is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP makes use of an architecture where a number of simple processors are tiled across a single chip and connected by a fast interconnection network. The system is designed …
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High Performance Applications for the Single-Chip Message-Passing Parallel Computer
… to the aforementioned challenges is the Single-Chip Message-Passing (SCMP) Parallel Computer, developed at Virginia Tech. SCMP is a unique, tiled architecture aimed at thread-level parallelism (TLP). Identical cores are replicated across the chip, and global wire traces have been eliminated. The …
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Silicon Photonics for All-Optical Processing and High-Bandwidth-Density Interconnects
… rack, and facility levels. While networks on chip for chip multiprocessors (CMP) were initially deemed the target application of silicon photonic components, it has become evident in recent years that the initial lower hanging fruit is the CMP's I/O links to memory as well as other CMPs. The …