Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 24 for “"Cache memory."”.
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Scalable primary cache memory architectures
… of this trend has included the growth of on-chip caches which in modern processor can be as large as 2MB. However, as smaller technologies become prevalent, achieving low average memory access time by simply scaling existing designs becomes more difficult because of process limitations. This …
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Analyzing and improving cache memory instruction
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2025-08-01
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Cache memory management in real-time systems
… of performance and predictability. Although memory caching has long been known as a means of increasing system performance, it is typically unpredictable in nature.
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Accurate Low-Cost Methods for Performance Evaluation of Cache Memory Systems
… simulation is a simple way of evaluating cache memory systems with varying hardware parameters. But to evaluate realistic workloads, simulating even a few million addresses is not adequate and such large scale simulation is impractical from the consideration of space and time requirements. …
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Toward time-predictable execution of multi-task real-time systems
… but also other supportive components such as cache memory, network on chip (NoC), memory controllers. These three components are designed to improve the system computational throughput through either bringing data closer to the processors (e.g cache memory) or maximizing concurrency in moving …
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Formal Specification and Runtime Verification of Parallel Systems using Interval Temporal Logic (ITL)
… as a demonstration, the case study of private L2 cache memory of multi-core processor architecture. My objectives are to i) design MSI protocol compliant with cache memory coherence and ii) fulfil main memory consistency model at runtime. I achieve this via a formal Tempura specification of the …
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Shared Cache Organization for Multiple-Stream Computer Systems
Organizations of shared two-level memory hierarchies for parallel-pipelined multiple instruction stream processors are studied. The multicopy of data problems are totally eliminated by sharing the caches. All memory modules are assumed to be identical and cache addresses are interleaved by sets. …
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Mitigation of Cache Attacks on Cloud Services
… issues to cloud service providers and customers. Cache attacks are a critical security risk in cloud computing. Cache attacks use weaknesses in cloud servers' cache memory to steal sensitive information, interrupt services, and decrease cloud performance. This study examines the many forms of …
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TEMPERATURE AND LEAKAGE AWARE TECHNIQUES TO IMPROVE CACHE RELIABILITY
… of the most critical design concerns. On-chip cache memories dominate the chip area in microprocessors and thus arises the need for power efficient cache memories. Cache is the simplest cost effective method to attain high speed memory hierarchy and, its performance is extremely critical for …
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Compiler-directed cache coherence strategies for large-scale shared-memory multiprocessor systems
The cache coherence maintenance problem has been the major obstacle in using private cache memory to reduce memory access latency in large-scale multiprocessor systems. Two compiler-directed solutions, the fast selective invalidation scheme and the version control scheme, are proposed in this work. …
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An Empirical Evaluation of Multi-Resource Scheduling for Moldable Workflows
… diverse set of resources (e.g., computing cores, cache, memory, I/O, and network resources) in the design of run-time schedulers for improving the overall application performance. This thesis performs an empirical evaluation of a recently proposed multi-resource scheduling algorithm for minimizing …
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Maximizing Cache Value For Distributing Content Via Small Cells In 5G
… of these encoded symbols should be placed in SC caches to facilitate efficient download. The main objective of this thesis is to develop an algorithm of low complexity to determine the number of encoded symbols of each file that should be cached at each SCs as a function of cache size. Each file …
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Cache Characterization and Performance Studies Using Locality Surfaces
Today's processors commonly use caches to help overcome the disparity between processor and main memory speeds. Due to the principle of locality, most of the processor's requests for data are satisfied by the fast cache memory, resulting in a signficant performance improvement. Methods for …
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Configuring In-Memory Caches: From TTL-Aware Sizing to Interval-Based Historical Analysis with HistoChron
In-memory caches such as Memcached and Redis are crucial for enhancing the performance of distributed systems by significantly reducing query response times. Correctly sizing these caches is critical, especially considering that prominent organizations use terabytes to petabytes of Dynamic Random …
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General-purpose Reconfigurable Functional Cache architecture
… to the idea of reconfigurability. Reconfigurable cache architecture gives us the flexibility to dynamically alter the execution logic of a processor, customized to a specific application. Reconfigurable Functional Cache Architecture uses a dynamic resource configuration of on-chip cache memory by …
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High Performance Large Graph Analytics by Enhancing Locality
… the phenomenon of frequently accessing the same memory location or adjacent memory locations. Applications with poor data locality reduce the effectiveness of the cache memory. They result in large number of cache misses, requiring access to high latency main memory. Therefore, it is essential to …
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Improving the Off-chip Bandwidth Utilization and Energy Efficiency in Chip Multiprocessor (CMP) Architectures
… the early write-back technique for a two-level cache hierarchy in a CMP with four processor cores. Early write-back can be viewed as a modified cache write policy that takes into account not only maintaining data consistency between on-chip and off-chip components of the memory hierarchy but …
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Building high-performance and versatile data plane for modern data center network
Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-11-15 without embargo terms
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