Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 15 of 15 for “"Cache hierarchy"”.
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Locality-aware cache hierarchy management for multicore processors
… number of cores in conventional directory-based cache coherence protocols. Another major challenge is limited cache capacity and the data movement incurred by conventional cache hierarchy organizations when dealing with massive data scales. These two factors impact memory access latency and …
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Refrint: intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies
… given that, intuitively, the large multi-level cache hierarchy of a manycore is likely to contain a lot of useless data. An effective way to reduce this problem is to use a low-leakage technology such as embedded DRAM (eDRAM). However, such systems require refresh. In this paper, we examine the …
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Computing with Spintronics: Circuits and architectures
… to realize the different levels in the memory hierarchy of the domain-specific processor, based on their respective access characteristics. Architectural tradeoffs created by the use of spintronic memories are analyzed. The proposed design achieves 1.5X-4X improvements in energy-delay product …
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Cache-based side channels: Modern attacks and defenses
… side channel attacks that exploit the shared cache hierarchies. Recently, we have witnessed ever more effective cache-based side attack techniques and the serious security threats posed by these attacks. It is urgent for computer architects to redesign processors and fix these vulnerabilities …
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Run-Time Adaptive Cache Management
The objective of this dissertation is to improve cache effectiveness, taking advantage of the growing chip area, utilizing run-time adaptive cache management techniques, and optimizing both performance and cost of implementation. Specifically, the aim is to increase cache effectiveness for integer …
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Architecting, programming, and evaluating an on-chip incoherent multi-processor memory hierarchy
… and proposes a cluster-based on-chip memory hierarchy without hardware cache coherence. Programming for such an environment, which can use scratchpads or incoherent caches, is challenging. Hence, this thesis focuses on architecting, programming, and evaluating an on-chip incoherent …
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High-performance memory safety - Optimizing the CHERI capability machine
… to increased memory bandwidth requirements and cache pressure when using CHERI capabilities in place of conventional 64-bit pointers. In order to mitigate this cost, I present two new 128-bit CHERI capability formats, using different compression techniques, while preserving C-language …
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Modular verification of hardware systems
… with the memory system employing an arbitrary hierarchy of cache nodes that communicate with each other concurrently, and with the processor doing speculative execution of many concurrent read operations. Nonetheless, we prove that the combined system implements sequential consistency. To our …
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Zero-Copy Communication for Efficient Compound Processes
… introduce user–kernel transitions, disturb caches, and repeatedly copy data, overheads that quickly become dominant in data-intensive workloads. The Compound Processes framework reduces some of these costs by allowing multiple cooperating guests to run inside a shared, trusted environment, …
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Analytical Query Processing Based on Continuous Compression of Intermediates
… RAM and CPU over a better utilization of the cache hierarchy to fast direct processing of compressed data. However, compression also incurs a certain computational overhead. State-of-the-art systems focus on the compression of base data. However, intermediate results generated during the …
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Workload-aware compressed linear algebra for data-centric machine learning pipelines
… memory, reducing I/O across the storage-memory-cache hierarchy, decreasing energy consumption, and increasing instruction parallelism. Modern machine learning (ML) systems exploit the approximate nature of ML and mostly use lossy compression via low-precision floating- or fixed-point quantized …
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Reducing Cache Contention On GPUs
… over traditional CPU-based implementations. Caches, which significantly improve CPU performance, are introduced to GPUs to further enhance application performance. However, the effect of caches is not significant for many cases in GPUs and even detrimental for some cases. The massive …
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Improving the Off-chip Bandwidth Utilization and Energy Efficiency in Chip Multiprocessor (CMP) Architectures
… the early write-back technique for a two-level cache hierarchy in a CMP with four processor cores. Early write-back can be viewed as a modified cache write policy that takes into account not only maintaining data consistency between on-chip and off-chip components of the memory hierarchy but …
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Cache design exploration in a general purpose massively parallel architecture
Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated …
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Power and energy management of modern architectures in adaptive HPC runtime systems
… illustrate that some system components such as caches and network links consume extensive power disproportionately for common HPC applications. We demonstrate how a large fraction of power consumed in caches and networks can be saved using our approach automatically. In these cases, the hardware …