Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Cache design"”.
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Cache design exploration in a general purpose massively parallel architecture
Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated …
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Cache Design and Performance in a Large-Scale Shared-Memory Multiprocessor System
The use of a private cache in each processor of large-scale shared-memory multiprocessor systems can reduce long global memory latency but also introduces the cache coherence problem. Cache design and performance in a large-scale multiprocessor are affected by the cache coherence problem and the …
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Design and analysis of spatially-partitioned shared caches
… CMPs devote more than half their area to on-chip caches. Moreover, these costs are increasing as CMPs scale to larger core counts. Processors rely on the on-chip caches to limit data movement, but CMP cache design is challenging. For efficiency reasons, most cache capacity is shared among cores …
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Cache Characterization and Performance Studies Using Locality Surfaces
Today's processors commonly use caches to help overcome the disparity between processor and main memory speeds. Due to the principle of locality, most of the processor's requests for data are satisfied by the fast cache memory, resulting in a signficant performance improvement. Methods for …
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Co-design of on-chip caches and networks for scalable shared-memory many-core CMPs
… architecture for the many-core era, on-chip cache organization and coherence are far from solved problems. As the on-chip interconnect directly influences the latency and bandwidth of on-chip cache, scalable interconnect is an essential part of on-chip cache design. On the other hand, optimal …
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In-Memory Computing Architecture for Deep Learning Acceleration
… for model training in the accelerators, large cache demands for multi-core processors, system performance, energy, and efficiency. In this thesis, I present my research works that address these challenges by leveraging emerging memory and logic devices, as well as advanced integration …
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Proximity coherence for chip-multiprocessors
… and latency costs of communication. Existing designs provide a functional communication layer but do not necessarily implement the most efficient solution for chip-multiprocessors, placing limits on the performance of these complex systems. In an era of increasingly power limited silicon …