Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 19 of 19 for “"Cache Coherence Protocol"”.
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Verification and Performance of the DeNovo cache coherence protocol
… to formally verify and evaluate the DeNovo cache coherence protocol. By using a model checking tool, we uncovered three bugs in the protocol implementation which had not been found either in the testing phase or in the simulation runs. All of these bugs were caused by errors in translating …
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Rapid designs for cache coherence protocol engines in Bluespec
… this thesis, we present the framework for Rapid Protocol Engine Development (RaPED). We implemented the framework in Bluespec, which is a high level hardware language based on Term Rewriting Systems (TRSs). The framework is highly parameterized and general, thus allowing designers to design any …
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Hardware implementation and evaluation of the Spandex cache coherence protocol
… bring the need for efficient and flexible cache coherence support. Since different devices like CPUs, GPUs and accelerators have diverse memory demands and different data-sharing patterns, Spandex was proposed to efficiently integrate devices with different cache coherence protocols. The …
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ATAC : A 1000-core cache coherent processor with on-chip optical network
… with integrated optics, and ACKwise, a novel cache coherence protocol designed to leverage ATAC's strengths. ATAC uses nanophotonic technology to implement a fast, efficient global broadcast network which helps address a number of the challenges that future multicores will face. ACKwise is a …
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Synchronization in timestamp-based cache coherence protocols
… support hundreds or thousands of cores. A cache coherence protocol manages the memory cached by these many cores, but the storage overhead required by existing directory-based protocols to track coherence state scales poorly as the number of cores increases. The Tardis cache coherence …
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Cache Coherence in Embedded -Ring Multiprocessors
… and, as a result, provide simple and competitive cache coherence protocol designs.
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Synchronization, coherence, and consistency for high performance shared memory multiprocessing
… multiprocessor architecture, an adaptive cache coherence protocol, and efficient and simple synchronization support that together meet this challenge. We have also developed an execution-driven tool for the simulation of shared-memory multiprocessors, which we use to evaluate the proposed …
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Cache coherent commutative operations
… systems. In particular, it describes a new cache coherence protocol, MEUSI, and evaluates its performance under simulation in zsim. MEUSI extends the MESI protocol to allow data to be cached in a new update-only state, reducing both block-level thrashing and on-chip network traffic under …
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Logical leases : scalable hardware and software systems through time traveling
… leverages logical leases to implement a scalable cache coherence protocol for multicore shared-memory processors. Compared to the widely-adopted directory-based cache coherence protocol, and its variants, Tardis avoids multicasting and broadcasting and only requires [theta](logN) storage per cache …
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Scalable and flexible bulk architecture
… detecting SC violations in a directory-based cache coherence protocol precisely. For chunk-based execution to be competitive, a machine must support chunk operations very efficiently. In my research, I focus on an environment with lazy conflict detection. In this environment, a major …
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Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors
… specifications, and 3) designing scalable coherence protocols.</p> <p>First, we propose CCA, a new design paradigm for increasing the processor's lifetime performance in the presence of permanent faults in cores. CCA chips rely on a reconfiguration mechanism that allows cores to replace …
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Efficient Virtual Cache Coherency for Multi-core Systems and Accelerators
… with existing userspace software. A virtual cache coherence protocol can be helpful for such task, allowing individual components to perform virtual address accesses without having to include their own hardware for address translation and memory protection. This thesis presents such a …
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Studying and Analysing Transactional Memory Using Interval Temporal Logic and AnaTempura
… a chip-dual single-cycle MIPS processor with a cache coherence protocol and integrate the provable TM system. Finally, we transform the dual processors with the TM from a high-level description into a Hardware Description Language (VHDL), using some proposed refinement and restriction rules. …
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Hardware-level fine-grained thread migration
… to moving threads across processors and loss of cache affinity, assigning threads to specific processor cores for long periods has remained the default strategy for ensuring maximum performance. Massive-scale single-chip multiprocessors dramatically alter this picture. On-chip data transfer …
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Optimizing communication bottlenecks in multiprocessor operating system kernels
… one core and read or written on other cores, the cache coherence protocol serializes accesses to the data. The result is that each access to the shared data can take hundreds to thousands of cycles, depending on how many cores are contending for the data. This dissertation focuses on optimizing …
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Efficient coherence and consistency for specialized memory hierarchies
… (1) a unified global address space, (2) the cache coherence protocol, and (3) the memory consistency model. A unified global address space makes it easier to write programs for heterogeneous systems. Although industry has recently begun to provide a unified global address space across CPUs …
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Modular verification of hardware systems
… system employing an arbitrary hierarchy of cache nodes that communicate with each other concurrently, and with the processor doing speculative execution of many concurrent read operations. Nonetheless, we prove that the combined system implements sequential consistency. To our knowledge, our …
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Effective architectural support for detecting concurrency bugs
… machine with a relaxed memory model, we leverage cache coherence protocol transactions and dynamically detect cycles in memory-access orderings across threads. When one such cycle is about to occur, an exception is triggered, providing the exact architectural state. We performed detailed …
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Record and deterministic replay of parallel programs on multiprocessors
… in parallel without making any changes to the cache coherence protocol and messages. The proposal uses a novel hybrid hardware/software mechanism for recording memory access interleaving. The hardware component records a raw and incomplete log that is then processed and transformed into a …