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Showing 1 to 20 of 188 for “"CPUs"”.

  1. Very High Frequency Integrated POL for CPUs

    … are widely used in almost all kinds of CPUs, ranging from the big servers in data centers to the small smartphones in almost everyone's pocket. When powering multiple processor cores, the energy consumption can be reduced dramatically if the supply voltage can be modulated rapidly based …

    vt Repository record for Very High Frequency Integrated POL for CPUs (opens in a new tab)

  2. Métodos para caracterização de desempenho de CPUs industriais

    … de sistemas de controle baseados em CLPs e CPUs Industriais. O processo de avaliação de desempenho e discutido em todas as etapas, desde o estudo da aplicação at e a execução dos passos de caracterização de desempenho. Para ilustrar a aplicação das métricas, técnicas e procedimentos …

    brazil-ufrgs Repository record for Métodos para caracterização de desempenho de CPUs industriais (opens in a new tab)

  3. Dynamic loop vectorization for executing OpenCL kernels on CPUs

    … in supercomputing. Many systems now integrate CPUs and GPUs cooperating together on a single node. Much effort is invested in tuning GPU-kernels. However, it can be the case that some systems may not have GPUs or the GPUs are busy. Maintaining two versions of the same code for GPUs and CPUs is …

    uiuc Repository record for Dynamic loop vectorization for executing OpenCL kernels on CPUs (opens in a new tab)

  4. Accelerating graph attention network inference on CPUs with layer fusion

    Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2026-05-01

    uiuc Repository record for Accelerating graph attention network inference on CPUs with layer fusion (opens in a new tab)

  5. Exploiting and coping with sparsity to accelerate DNNs on CPUs

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2022-04-06 without embargo terms

    uiuc Repository record for Exploiting and coping with sparsity to accelerate DNNs on CPUs (opens in a new tab)

  6. A tiered network buffer architecture for fast networking in chiplet-based CPUs

    Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2027-05-01

    uiuc Repository record for A tiered network buffer architecture for fast networking in chiplet-based CPUs (opens in a new tab)

  7. Modeling of a buck converter with fast load transient auxiliary circuit for CPUs

    In a buck converter, the output capacitance is the dominant factor that determines the magnitude of overshoot/undershoot in the supply voltage during a load transient. In applications such as powering a CPU, the CPU can make computational predictions for its future supply current levels which can …

    uiuc Repository record for Modeling of a buck converter with fast load transient auxiliary circuit for CPUs (opens in a new tab)

  8. Impact of shipping Ball-Grid-Array Notebook processors in tape and reel on the PC supply chain

    … such a thin form factor, PGA (Pin Grid Array) CPUs must now be offered as BGA (Ball Grid Array) CPUs to reduce the height of one of the taller items of the system. With the increased number of Ultrabooks [TM] being offered, the overall volume of BGA CPUs shipped by Intel is expected to …

    mit Repository record for Impact of shipping Ball-Grid-Array Notebook processors in tape and reel on the PC supply chain (opens in a new tab)

  9. SNIC-DSM: SmartNIC based DSM Infrastructure for Heterogeneous-ISA Machines

    … Heterogeneous hardware typically includes CPUs, GPUs, ASICs, and FPGAs, among others. An important emerging trend is instructionset- architecture (ISA)-heterogeneity: high-end x86 servers with attached SmartNICs and SmartSSDs that incorporate general-purpose CPUs, typically of the RISC ISA …

    vt Repository record for SNIC-DSM: SmartNIC based DSM Infrastructure for Heterogeneous-ISA Machines (opens in a new tab)

  10. ZxOS: Zephyr-based Guest Operating System for Heterogeneous ISA Machines

    … such as SmartNICs and SmartSSDs that incorporate CPUs of the RISC ISA family (e.g, ARM64, RISC-V), which when integrated with a highperformance server with CPUs of the CISC ISA family (e.g., x86-64) yields a single machine with heterogeneous-ISA CPUs. This thesis presents the design of a shared …

    vt Repository record for ZxOS: Zephyr-based Guest Operating System for Heterogeneous ISA Machines (opens in a new tab)

  11. Heterogeneous CPU-FPGA system framework and scheduler

    … that consist of general-purpose units such as CPUs, and specialized accelerators, such as FPGAs, to boost computational efficiency and throughput. Our research centers on exploiting the multithreading of CPUs and the pipelined architecture of FPGAs. We specifically focus on the distribution of …

    uiuc Repository record for Heterogeneous CPU-FPGA system framework and scheduler (opens in a new tab)

  12. Functional level modeling of digital devices

    … RAMs, ROMs, microprocessor peripheral chips and CPUs. Processors modeled include the Intel 8080, the Zilog Z80 (single chip CPUs) and the Bendix BDX930 (MSI).

    vt Repository record for Functional level modeling of digital devices (opens in a new tab)

  13. Local Signal Processing of the ALICE Transition Radiation Detector at LHC (CERN)

    … they are analyzed by a preprocessor and four CPUs with respect to segments of tracks. The thesis covers the complete development from hardware design of filter and preprocessor, their calibration, programming of the CPUs, up to first application studies on a prototype system.

    heid-diss Repository record for Local Signal Processing of the ALICE Transition Radiation Detector at LHC (CERN) (opens in a new tab)

  14. AN EQUIVALENT CLASS SOLUTION FOR A COMPLETE TEST OF A PARALLEL PROGRAM

    With the advent of multi-core chips (multiple CPUs on a single chip) a fundamental shift in the design of programs is taking place. Previous use of parallel code in programs was limited to servers that contained multiple CPUs on separate chips. This idea is starting to change, with the majority of …

    montana-tech Repository record for AN EQUIVALENT CLASS SOLUTION FOR A COMPLETE TEST OF A PARALLEL PROGRAM (opens in a new tab)

  15. AN EQUIVALENT CLASS SOLUTION FOR A COMPLETE TEST OF A PARALLEL PROGRAM

    With the advent of multi-core chips (multiple CPUs on a single chip) a fundamental shift in the design of programs is taking place. Previous use of parallel code in programs was limited to servers that contained multiple CPUs on separate chips. This idea is starting to change, with the majority of …

    montana Repository record for AN EQUIVALENT CLASS SOLUTION FOR A COMPLETE TEST OF A PARALLEL PROGRAM (opens in a new tab)

  16. Parallel fluid dynamics for the film and animation industries

    … environments making use of hundreds or more CPUs have been used. This overcomes the processing power and memory limitations of a single computer and allows very large scenes to be created. One of the newer methods for fluid simulation is the Lattice Boltzmann Method (LBM). This is a cellular …

    cape-town Repository record for Parallel fluid dynamics for the film and animation industries (opens in a new tab)

  17. Network assisted file system consistency checking

    … for NAN's performance. On machines with four CPUs, the running time of NAN was within 1% of the running time of NFSCK. On machines with two CPUs, running time was up to 6% worse with a large file data set, and up to 22% worse with a small file data set.

    mit Repository record for Network assisted file system consistency checking (opens in a new tab)

  18. CUDA Enhanced Filtering In a Pipelined Video Processing Framework

    … frame data is growing ever larger.</p> <p>Modern CPUs offer performance enhancements for processing digital video through SIMD instructions such as SSE2 or AVX. However, even with these instruction sets, CPUs are limited by their inherently sequential design, and can only operate on a handful of …

    calpoly Repository record for CUDA Enhanced Filtering In a Pipelined Video Processing Framework (opens in a new tab)

  19. Combustion Simulations Using Graphic Processing Units

    … validated with the results from simulations with CPUs using detailed mechanisms of various fuels including H<sub>2</sub>, and CH<sub>4</sub>. It was found that the GPU-accelerated simulations can be approximately 10-20 times faster than those on CPUs for solving identical problems. Furthermore, …

    uconn-diss Repository record for Combustion Simulations Using Graphic Processing Units (opens in a new tab)

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