Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 18 of 18 for “"CMOS VLSI"”.
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iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Very large scale integrated (VLSI) circuit technology allows one to manufacture chips with several million devices. Designing such large circuits cannot be accomplished without design automation tools and computer-aided design tools. This thesis addresses the problem of automatic circuit synthesis …
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CMOS VLSI implementation of the Quick Look Global Positioning System
Thesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1992.
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Electrothermal Simulation and Temperature-Sensitive Reliability Diagnosis for CMOS VLSI Circuits
ILLIADS-T has been successfully applied to the electromigration (EM) reliability diagnosis and timing analysis. By considering both transistor and interconnect temperatures, the temperature-sensitive EM-induced mean time-to-failure and critical path timing are estimated and discussed.
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Test generation and evaluation for bridging faults in CMOS VLSI circuits
… generator for I$\sb{DDQ}$ current testing of CMOS digital circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.
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Worst case voltage drops in power and ground buses of CMOS VLSI circuits
… flowing in the power and ground (P&G) buses of CMOS digital circuits affect both circuit reliability and performance by causing excessive voltage drops. Excessive voltage drops manifest themselves as glitches on the P&G buses and cause erroneous logic signals and degradation in switching speeds. …
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Wafer bonding of processed Si CMOS VLSI and GaAs for mixed technology integration
… making it compatible with a fully processed SOI CMOS wafer. The use of dielectric CMP has become a common back-end processing step. The wafer bonding in this work relies on CMP technology to planarize PECVD oxide deposited on the bonding surface of both wafers. The combination of CMP with post …
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Wafer bonding for monolithic integration of Si CMOS VLSI electronics with III-V optoelectronic devices
… wafers are suitable for the fabrication of Si SOICMOS electronics and the subsequent monolithic integration of high performance optoelectronic devices. Future goals for this work include bonding fully processed SOI-CMOS wafers to the GaAs, rather than silicon wafers containing no electronics. With …
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Modeling and simulation ofpMOSFET hot-carrier degradation in very large CMOS circuits
… tool for hot-carrier reliability analysis of CMOS VLSI circuits. This simulator should be able to handle very large submicrometer circuits accurately and efficiently.
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A simulation and redesign system for circuit hot-carrier reliability
In this thesis a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates circuits to determine the critical transistors that are most susceptible to hot-carrier effect (HCE); it then estimates the impact of HCE on …
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Design and implementation of three-dimensional logic structures
… to those familiar with two-dimensional CMOS VLSI design. This software system provides desirable features such as SPICE circuit extraction and the ability to produce the design formats necessary for automated fabrication (e.g. mask specifications for lithography or Gerber data for inkjet …
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Optimization of high-speed CMOS circuits with analytical models for signal delay
… optimization of high speed and high integration CMOS VLSI circuit is greatly in need in deep submicron regime with respect to signal delay, chip area and power dissipation. Accurate modeling of signal path delays is of particular importance in optimization. Although circuit level simulators like …
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Techniques for low power analog, digital and mixed signal CMOS integrated circuit design
… power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in …
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Accelerating the parsing process with an Application Specific VLSI RISC processor
… physical implementation of a RISC processor in CMOS VLSI technology able to execute the designed instruction set. The feasibility of mapping the process of language recognition onto the instruction set of a RISC processor is investigated. This involves an assessment of the suitability of the …
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High Speed Circuit Design Based on a Hybrid of Conventional and Wave Pipelining
… speed is short signal rise and fall times. Since CMOS wide-NAND and wide-NOR gates exhibit long rise and fall times and large delay variations, they should be decomposed. We show that the straightforward decomposition using alternating levels of NAND and NOR gates results in large delay …
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Fast Approximation Framework for Timing and Power Analysis of Ultra-Low-Voltage Circuits
Ultra-Low-Voltage operation, which can be considered an extreme case of voltage scaling, can greatly reduce the power consumption of circuits. Despite the fact that Ultra-Low-Voltage operation has been proven to be very effective by several successful prototypes in recent years, there is no fast, …