Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 18 of 18 for “"Built-in Self Test (BIST)"”.
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On fault coverage and fault simulation for multiple signature analysis BIST schemes
… related to multiple signature analysis (MSA) built-in self-test (BIST) schemes are treated here. A model to predict the fault coverage is presented. Based on this model, the nature of the fault coverage for MSA is discussed. The fault coverage of MSA is a function of both the signature sizes …
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A SEIR-based ADC built-in-self-test and its application in ADC self-calibration
The static linearity test is one of the fundamental production tests used to measure DC performance of analog to digital converters (ADCs). It comes with high test equipment cost. An ADC built-in-self-test (BIST) is an attractive solution. However the stringent linearity requirement for an on-chip …
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In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs
… recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors …
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Testing and Fault-Tolerance Aspects of High-Density VLSI Memory
Presented in this thesis is a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for RAMs and CAMs are developed for a broad class of …
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New Techniques for Logic Built -in Self -Test
The dissertation investigates new techniques for logic built-in self-test (BIST) in VLSI chip testing. The main purpose of these techniques is to improve fault coverage for logic BIST with minimal performance penalty and hardware overhead. One technique is the method of constrained scan cells. It …
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Novel methods for post-manufacturing and in-field testing of VLSI circuits/systems
In this work, at first we analyze and evaluate, the already known test data compression schemes for post-manufacturing testing and the DFT mechanisms for the enhancement of in-field testing and circuit reliability. We propose a new dictionary based test data compression method for …
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FIELD-PROGRAMMABLE MICROFLUIDIC TEST PLATFORM FOR POINT-OF-CARE DIAGNOSTICS
Early work in electrowetting on dielectric (EWOD) devices has demonstrated their great potential in microfluidics; however, further work is needed to integrate EWOD technology into a system deployable for point-of-care (POC) diagnostics. This research is aimed at providing enabling technologies …
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Low Power High Fault Coverage Test Techniques for Digital VLSI Circuits
Testing of digital VLSI circuits entails many challenges as a consequence of rapid growth of semiconductor manufacturing technology and the unprecedented levels of design complexity and the gigahertz range of operating frequencies. These challenges include keeping the average and peak power …
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A Complete & Practical Approach to Ensure the Legality of a Signal Transmitted by a Cognitive Radio
… to create a cognitive radio are quickly becoming available. There are many advantages to having a radio operated by cognitive engine, and so cognitive radios are likely to become very popular in the future. One of the main difficulties associated with the cognitive radio is ensuring the signal …
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Técnica baseada em contratos para a validação da comunicação de alto nível entre software e hardware
… erros devido à natureza do ambiente no qual está inserido e a sua difícil codificação, é importante que as fases de desenvolvimento e de operação destes componentes sejam suportadas por metodologias que tornem mais explícitas violações de acessos a dispositivos através do acompanhamento de de …
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Predicting performance parameters of analog and mixed-signal circuits using built-in and built-off self test
The widespread use of embedded mixed-signal cores in system-on-chip (SoC) or System-on-Package (SoP) design has been increasingly important in cost-effective manufacturing test for mixed-signal devices. A typical SoP encapsulates many of its internal functions, and its production test is performed …
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A truly embedded test structure for design-for-manufacturability, hardware security and VLSI testing
As the feature sizes continue to shrink in advanced VLSI technologies, the impact of process variations on yield losses has become significant. Moreover, the process variations in path delays are increasingly dependent on circuit context. Given this 'neighborhood' dependence, characterization of …
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Exploring Temporal and Spatial Correlations on Circuit Variables for Enhancing Simulation-based Test Generation
The ever-increasing complexity and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and …
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Integrated Enhancement of Testability and Diagnosability for Digital Circuits
While conventional test point insertions commonly used in design for testability can improve fault coverage, the test points selected may not necessarily be the best candidates to aid <em>silicon diagnosis</em>. In this thesis, test point insertions are conducted with the aim to detect more faults …
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High-Level Synthesis and Implementation of Built-In Self-Testable Data Path Intensive Circuit
A high-level built-in self-test (BIST) synthesis is a process of transforming a behavioral description into a register-transfer level structural description while minimizing BIST overhead. Existing high-level BIST synthesis methods focus on one objective, minimizing either area overhead or test …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked …
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METHODS TO MINIMIZE LINEAR DEPENDENCIES IN TWO-DIMENSIONAL SCAN DESIGNS
Two-dimensional scan design is an effective BIST architecture that uses multiple scan chains in parallel to test the Circuit Under Test (CUT). Linear Finite State Machines (LFSMs) are often used as on-board Pseudo Random Pattern Generators (PRPGs) in two-dimensional scan designs. However, linear …
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Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs
<p>With the continuous scaling of transistors to smaller dimensions, it has now become feasible to pack billions of transistors in a single chip. However, interconnect does not scale as well as transistors; hence a significant amount of research is focused today on finding viable alternatives to …