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Showing 1 to 3 of 3 for “"Buffered crossbar"”.

  1. Providing QoS guarantees in input buffered crossbar switches with speedup

    … providing Quality of Service guarantees in input-buffered crossbar switches with speedup. It is shown that speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. It is also demonstrated that the crossbar architecture is capable …

    mit Repository record for Providing QoS guarantees in input buffered crossbar switches with speedup (opens in a new tab)

  2. Architecture design and performance analysis of practical buffered-crossbar packet switches

    Combined input crosspoint buffered (CICB) packet switches were introduced to relax inputoutput arbitration timing and provide high throughput under admissible traffic. However, the amount of memory required in the crossbar of an N x N switch is N^2x k x L, where k is the crosspoint buffer size and …

    njit Repository record for Architecture design and performance analysis of practical buffered-crossbar packet switches (opens in a new tab)

  3. Design and stability analysis of high performance packet switches

    … and high speed rates. Combined input-crosspoint buffered (CICB) switches are an alternative to input-buffered (IB) packet switches to provide high-performance switching and to relax arbitration timing for packet switches with high-speed ports. A maximum weight matching (MWM) scheme can provide …

    njit Repository record for Design and stability analysis of high performance packet switches (opens in a new tab)