Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 7 of 7 for “"Buffer Insertion"”.
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Clock tree synthesis under aggressive buffer insertion
… clock tree routing algorithm integrated with buffer insertion, buffer sizing, and topology generation that is able to consider general buffer insertion locations. While previous work on buffered clock tree synthesis restricts potential buffer locations on merge nodes in the clock tree …
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VLSI Physical Design for Manufacturability and Reliability
… such as maze routing, timing analysis and buffer insertion, are discussed. Proposed algorithm can handle an arbitrary function of mean and variance of path weight instead of convex constraint needed for existing algorithms. In Chapter 5, buffer insertion under process variations is …
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Techniques for VLSI Circuit Optimization Considering Process Variations
… such as gate sizing, timing based placement and buffer insertion. The uncertainty due to process variations is modeled using interval valued fuzzy numbers and a fuzzy programming based optimization is proposed to improve circuit yield without significant over design. In addition to the …
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Discrete Gate Sizing Methodologies for Delay, Area and Power Optimization
… areas (such as placement, routing, layout, buffer insertion, timing analysis, etc.).</p>
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Stochastic shortest path algorithm based on Lagrangian relaxation
… in VLSI circuit design, such as timing analysis, buffer insertion, and maze routing, can be formulated as shortest path problems using a statistical graph model. The solution of any such graph problem will surely have a statistical distribution for its cost function value. The mean and variance, …
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Novel algorithms for fair bandwidth sharing on counter rotating rings
… on the advantages of ring networks, new buffer insertion techniques, such as Spatial Reuse Protocol (SRP), were introduced in early 2000s. As a result, a new standard known as IEEE 802.17 Resilient Packet Ring was defined in 2004 by the IEEE Resilient Packet Ring (RPR) Working Group. …
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New methods for electronic design automation problems
… During the timing optimization process, buffers can be used to speed up the circuit or serve as delay elements. In this dissertation, we study the hold-violation removal problem for a circuit-level design. Considering the challenges of industrial designs, discrete buffer sizes, accurate …