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Showing 1 to 6 of 6 for “"Bridging Faults"”.
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Efficient Testing for Bridging Faults in Digital Integrated Circuits
Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1998.
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Test generation and evaluation for bridging faults in CMOS VLSI circuits
… circuits is presented. The complete two-line bridging fault set is considered. Because of the time constraints of I$\sb{DDQ}$ testing, an adaptive genetic algorithm (GA) is used to generate compact test sets.
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Fault simulation for supply current testing of bridging faults in CMOS circuits
… a method for fault simulation that considers bridging faults in CMOS circuits that are tested using supply current monitoring. The discussion is restricted to single fault detection in CMOS combinational circuits. A CMOS circuit is represented by a two-level hierarchy. At the higher level, the …
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A Design Methodology for Physical Design for Testability
… in a way to avoid or reduce realistic physical faults. The goal of this work is to define and establish a speci c methodology for PDFT. The proposed design methodology includes techniques to reduce potential bridging faults in complementary metal-oxide-semiconductor (CMOS) circuits. To compare …
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Simulation- and Deduction-Based Techniques for Fault Diagnosis
… and dynamic processing for the diagnosis of bridging faults in sequential circuits is presented. During diagnosis, the failing outputs from the test are used to adaptively determine the behavior of the bridge at each time-frame. Selective faulty state information is stored by performing …
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Fault Simulation and Transistor-Level Test Generation for Physical Failures in Mos Circuits
… not applicable. In order to reduce the number of faults which need to be considered in the system so that the effort for test generation and fault simulation can be reduced, two fault collapsing techniques (inter-gate fault collapsing and intra-gate fault collapsing) for both nMOS and CMOS …