Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 18 of 18 for “"Bluespec"”.
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Bluespec Language Server: Adapting Rust Analyzer for Bluespec SystemVerilog
… or Pylance. However, smaller languages like Bluespec SystemVerilog, used in computer architecture classes at MIT, often need to make do without a language server. As students come to expect smart code editing features, they may miss the convenience when working with languages like Bluespec. …
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Designing a processor in Bluespec
… we designed a 2-way out-of-order processor in Bluespec implementing the MIPS I integer ISA. A number of scheduling optimizations were then used to bring the initial design up to the same level of cycle-level concurrency as found in standard RTL-level designs. From this, a general design …
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BlueVeri: Formal Security Verification for Bluespec Processor Designs
… for formally verifying the security of a Bluespec processor against speculative execution attacks. BlueVeri leverages the high-level information provided by Bluespec’s guarded atomic actions, simplifying and accelerating the verification process. We evaluate BlueVeri on out-of-order …
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Implementation of H.264 Decoder in Bluespec SystemVerilog
… a implementation of a H.264 decoder designed in Bluespec SystemVerilog, a high level hardware description language. This design is intended to serve both as a more understandable reference code, as well as a starting point for efficient hardware implementations. I illustrate this by modifying …
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Rapid designs for cache coherence protocol engines in Bluespec
… (RaPED). We implemented the framework in Bluespec, which is a high level hardware language based on Term Rewriting Systems (TRSs). The framework is highly parameterized and general, thus allowing designers to design any protocol engine in a short period. Since protocol engines can be …
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An FPGA implementation of multicore, multithreaded powerPC processors with memory subsystem using Bluespec
… memory units. All implementation was done in Bluespec System Verilog hardware synthesis language for placement on FPGA. Furthermore, this document analyzes the main tradeoffs and major challenges involved in building and integrating such a system.
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Comparison of high level design methodologies for algorithmic IPs : Bluespec and C-based synthesis
… time and allowing more algorithmic exploration. Bluespec is a Hardware Design Language (HDL) that allows designers to express intended microarchitecture through high-level constructs. C-based design tools directly generate hardware from algorithms expressed in C/C++. This research compares these …
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Design Methods for Cryptanalysis
… exploration required for optimization. First, Bluespec, a rule-based HDL, is used to increase the abstraction level of hardware design and support efficient design space exploration. Bluespec is applied to implement a hardware-accelerated logical attack on ECC with optimized modular arithmetic …
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An inlining approach to formal hardware semantics
… various hardware description languages (HDLs), Bluespec allows designers to develop hardware not only based on modularity, but also based on the notion of guarded atomic actions (GAAs). Following the concepts of modularity and GAA, we have been defining a framework called Kami to specify, …
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Modular verification of hardware systems
… verification of hardware designs written in the Bluespec language. That is, we formalize the idea of components in a hardware design, with well-defined input and output channels; and we show how to specify and verify components individually. For verifying a full system, we show how the proofs of …
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A methodology for hardware-software codesign
… of this thesis presents an implementation of the Bluespec Codesign Language (BCL) to address the difficulty of experimenting with hardware/software partitioning alternatives. Based on guarded atomic actions, BCL can be used to specify both hardware and low-level software. Based on Bluespec …
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Evaluating the Feasibility of Transaction Scheduling via Hardware Accelerators
… both an optimized software baseline and a Bluespec-based hardware design, evaluating their performance across synthetic YCSB-style workloads with varying contention levels. Our hardware prototype demonstrates competitive throughput, achieving over 90% of peak throughput even under …
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Design study of a novel computer instruction execution unit
… translated into hardware modules. The language Bluespec Verilog allows this description to be constructed in terms of higher-level "guarded atomic actions" triggered by a rule based system.
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A unified model for hardware/software codesign
… thesis addresses this problem by introducing, Bluespec Codesign Language (BCL), a united language model based on guarded atomic actions for hardware-software codesign. The model provides an easy way of specifying which parts of the design should be implemented in hardware and which in software …
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System specific power reduction techniques for wearable navigation technology
… newer OPT8320 evaluation platform, for which a Bluespec System Verilog implementation of these power algorithms and the point cloud generation operation is presented and tested. Overall, the work demonstrates the critical concept that simple, system specific, fully integrated algorithms can …
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Architectures for computational photography
… for the component modules are implemented using Bluespec SystemVerilog and verified to be bit accurate with a reference software implementation. Techniques to reduce power and area cost are investigated and synthesis results in 40nm CMOS technology are presented
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Modular SMT-Based Verification of Rule-Based Hardware Designs
… makes their design and verification difficult. Bluespec SystemVerilog (BSV) simplifies this problem by introducing the rule-level abstraction. Modules are expressed in terms of guarded atomic actions that appear to fire in a sequential order, even when multiple rules fire concurrently per clock …
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High-performance memory safety - Optimizing the CHERI capability machine
This work presents optimizations for modern capability machines and specifically for the CHERI architecture, a 64-bit MIPS instruction set extension for security, supporting fine-grained memory protection through hardware-enforced capabilities. The original CHERI model uses 256-bit capabilities to …