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Showing 1 to 1 of 1 for “"Bit line capacitance"”.
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Study of design tradeoffs of DRAM and SRAM memories, using HSPICE computer simulation
… cycle time, access delays, storage capacity, bit packing density, chip area and retention time. In this thesis, tradeoffs between cycle time, chip area, and storage size as reflected by bit line capacitance (Cbl) were studied as a function of particular design variables: memory cell …