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Showing 1 to 5 of 5 for “"Baud rate"”.

  1. Low-power and energy-efficient wireline receivers

    … recovery (CDR) circuit in the receiver. A sub-baud-rate CDR that can recover clock and data using only differential quarter-rate clocks is presented. A combination of eight samplers and an integrator recovers four data bits in each clock cycle. Four of the eight samplers are reused for phase …

    uiuc Repository record for Low-power and energy-efficient wireline receivers (opens in a new tab)

  2. Facilitating FPGA Reconfiguration through Low-level Manipulation

    … the circuit for generating the desired BAUD rate to adapt to the requirement of a remote UART receiver.

    vt Repository record for Facilitating FPGA Reconfiguration through Low-level Manipulation (opens in a new tab)

  3. Electromagnetic Interference Attacks on Cyber-Physical Systems: Theory, Demonstration, and Defense

    … trajectory of a UAV. The attacks are demonstrated on a fixed-wing unmanned aerial vehicle (UAV) during varying flight scenarios, and it is observed that the attacker can block or take control of the flight surfaces (e.g., aileron) which results in a crash of the UAV or a controllable change …

    vt Repository record for Electromagnetic Interference Attacks on Cyber-Physical Systems: Theory, Demonstration, and Defense (opens in a new tab)

  4. Blind Synchronization and Detection of Nyquist Pulse Shaped QAM Signals

    … receiver includes the estimation of the symbol rate, the roll-off factor of the filter, the optimal sample phase, the frequency offset, the phase offset and as well as the correction of frequency and phase offsets. The blind receiver is proposed for the cognitive radio applications. Cognitive …

    usf Repository record for Blind Synchronization and Detection of Nyquist Pulse Shaped QAM Signals (opens in a new tab)

  5. Design of energy efficient high speed I/O interfaces

    The student, Mrunmay Vyankatesh Talegaonkar, accepted the attached license on 2016-03-11 at 14:21.

    uiuc Repository record for Design of energy efficient high speed I/O interfaces (opens in a new tab)