Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 24 for “"BEOL"”.
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TOWARDS INTEGRATION OF GRAPHENE IN ADVANCED CMOS INTERCONNECT TECHNOLOGY
… graphene is ideally suited for back-end of line (BEOL) technology to boost the performance of on-chip copper (Cu) interconnects. However, the lack of BEOL compatible methods has stymied the true evaluation of Cu/graphene hybrid (Cu-G) technology. The objectives of this thesis proposal are to …
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High performance MoS₂ transistors based on wafer-scale low-temperature MOCVD synthesis
Among all the possible back-end-of-line (BEOL) solutions to improve the integration density and functionality of conventional silicon circuits, two-dimensional (2D) material devices are believed to be very promising, due to their high mobility, relatively large band gaps, atom-level thickness, …
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Low temperature heterogeneous integration of germanium on silicon
… must be integrated in the back-end-of-line (BEOL) of a CMOS process flow. BEOL integration introduces strict temperature requirements of T<450°C to prevent metal diffusion and oxidation of devices already on-chip. First, this thesis tackles BEOL-compatible active devices such as Ge-on-Si PDs …
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Resistive Switching Behavior in Low-K Dielectric Compatible with CMOS Back End Process
… standard processes employed in back-end-of-line (BEOL) interconnect fabrication. Based on this premise, the study of this thesis aims at assessing a possible co-integration of resistive switching (RS) cells with current BEOL technology. In particular, the issue is whether RS can be realized with …
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Germanium photodetectors on amorphous substrates for electronic-photonic integration
… of photonics in the back-end-of-line (BEOL) of a standard CMOS process enables the advantages of optical interconnects while benefiting from the low cost of monolithic integration. However, processing in the BEOL requires device fabrication on amorphous substrates, and constrains …
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Lab-to-Fab Monolithic 3D Integrated Carbon Nanotube Transistors: Scaling and Reliability
… monolithic 3D technology using back-end-of-line (BEOL) carbon nanotube FET (CNFET) + Resistive RAM (RRAM) stack over silicon CMOS that achieves comparable memory performance (read power, write energy/latency, endurance, retention, multiple bits-per-cell capability) in the same footprint as a …
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Design/System Technology Co-optimization of Gallium Nitride High Electron Mobility Transistors for Next-G 3DIC Heterogeneous Integration of Gallium Nitride and Si CMOS
… of a 3DIC consisting of GaN HEMTs and Si CMOS BEOL, in particular W-band GaN HEMTs, Si CMOS BEOL circuits in Intel16, and advanced packaging of dielets. The full chip continuum is investigated and innovated upon.
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Impact of Thermal Effects and Other Material Properties on the Performance and Electro-Thermal Reliability of Resistive Random Access Memory Arrays
… Metal-oxide Semiconductor) Back-end of Line (BEOL), ReRAM stands as a leading candi- date for the next generation of non-volatile memory (NVM). ReRAM devices feature nanoionics-based filamentary switching, outperforming flash memory in terms of power consumption, scalability, retention, ON/OFF …
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Two-dimensional transition metal dichalcogenides as next generation semiconductor materials
… use of TMDs for the 3D back end of line (BEOL) integration of logic and memory and it investigates some of these challenges to help bridge the gap in the knowledge to strive for the reality of 3D BEOL. One of the approaches examined in this thesis is the mechanical exfoliation of TMD …
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Electrodeposition of Cobalt for Advanced Interconnect Applications
… have been used to produce back end of line (BEOL) interconnect structures in integrated circuits (IC). As the critical dimension of BEOL structures approaches the electron mean free path of Cu or below, the Cu resistivity exponentially increases, posing significant challenges on further …
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Study of CMOS process variation by multiplexing analog characteristics
… both NMOS and PMOS MOSFETs. Back end of line (BEOL) test structures include parasitic coupling, plane to plane and crossover capacitances, measured using a charge-based capacitive measurement (CBCM) methodology integrated with switches in the scan chain. The testing of the designed test chip …
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Impact of Inert-electrode on the Performance and Electro-thermal Reliability of ReRAM Memory Array
… for industrial production, a Back End of Line (BEOL)-compatible replacement of Pt is highly desirable. A systematic investigation has been conducted and metals such as Ru, Rh and Ir are found to be the best potential candidates to supplant Pt. The device properties of Ru, Rh and Ir based …
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Resistive Switching in Porous Low-k Dielectrics
… and logic closer by integrating memory in the BEOL. Resistive RAM is one such memory is not transistor based and thus, does not require a silicon substrate. Thus, it offers the possibility of integration directly into the back-end reducing memory to logic distance from 1000s of µm to a 10s of …
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Low-Temperature Germanium Waveguides for Mid-Infrared Sensing Applications
… for mid-IR waveguides. For back-end-of-line (BEOL) integration of waveguides in sensing applications, the thermal budget limits the temperature to below 450°C. In this work, we investigated the use of h-line exposure as a commercially viable, low-cost option for patterning low temperature (LT) …
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Integrated Heteroepitaxial Photodetectors
… and incorporation in the back-end-of-line (BEOL) stack, low processing temperatures (< 450°) are required. Using novel processing methods and strategic anneals, we have demonstrated that low temperature Ge growths on silicon can achieve low defect densities required for high performance. In …
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Design and Reliability of mm-Wave Circuits In Silicon-Germanium
… (FEOL: active devices) and Back End of the Line (BEOL: metal stack-up) in a commercial SiGe BiCMOS processes. The resulting performances utilize novel design techniques that allow them to be competitive with existing state-of-the-art designs across multiple IC technologies. The second goal of this …
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Monolithically integrated MEMS resonators and oscillators in standard IC technology
… (PnC) implemented in the CMOS back-end-of-line (BEOL) layers along with the bulk wafer are used to create a phononic waveguide. The latter confines acoustic vibrations in the CMOS front-end-of-line (FEOL) layers. Operator-theoretic analysis for these waveguides is presented in explicit analogy to …
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Advanced modeling of planarization processes for integrated circuit fabrication
… for device isolation and in back-end-of-line (BEOL) processing for interconnection. This thesis studies the physical mechanisms and variations in the planarization using chemical mechanical polishing (CMP). The major achievement and contribution of this work is a systematic methodology to …
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Characterization and performance analysis of a cognitive routing scheme for a metropolitan-area sensor network
This MEng thesis is an exploration of the notion of cognitive methods for routing in a network, and the resulting potential for improvements in network performance. In cognitive routing, individual network nodes gain information about the state of the network in a distributed fashion, by measuring …
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