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Showing 1 to 12 of 12 for “"Automatic Test Pattern Generation"”.
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COPING WITH DISCREPANCIES OF THE MANUFACTURED WEIGHTS IN THRESHOLD LOGIC GATES
… model for weight defects is proposed. Also an Automatic Test Pattern Generation (ATPG) tool has been implemented that uses the fault model to detect whether the circuit is malfunctioning due to such weight-related defects. A novel design methodology is presented in this work to design complex …
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SYNTHESIS AND TESTING OF THRESHOLD LOGIC CIRCUITS
… This renewed the interest in synthesis and testing of circuits with threshold logic gates. Two important synthesis considerations of threshold logic circuits are addressed namely, threshold logic function identification and reducing the total number of threshold logic gates required to …
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Design for Testability Techniques to Optimize VLSI Test Cost
High test data volume and long test application time are two major concerns for testing scan based circuits. The Illinois Scan (ILS) architecture has been shown to be effective in addressing both these issues. The ILS achieves a high degree of test data compression thereby reducing both the test …
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On Enhancing Deterministic Sequential ATPG
… performance of deterministic sequential circuit Automatic Test Patterns Generators (ATPG). Three techniques make use of information gathered during test generation to help identify more unjustifiable states with higher percentage of "don't care" value. An approach for reducing the search space of …
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ATPG and DFT Algorithms for Delay Fault Testing
… and increasing clock rate on chips, delay testing is becoming a necessity in industry to maintain test quality for speed-related failures. The purpose of delay testing is to verify that the circuit operates correctly at the rated speed. However, functional tests for delay defects are …
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Functional timing analysis of VLSI circuits containing complex gates
… account, one must exercise all possible input patterns. Obviously, this is not possible to accomplish due to the high complexity of current designs. To circumvent this problem, designers must rely on timing analysis. Timing analysis is an input-independent verification approach that models each …
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Exploring Temporal and Spatial Correlations on Circuit Variables for Enhancing Simulation-based Test Generation
… and size of current circuit designs have made testing and verification major bottlenecks in the design flow of VLSI (Very Large Scale Integrated) circuits. Statistics show that more than 70% of the design effort can be spent on functional verification and manufacturing testing. This percentage …
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Strategies for Performance and Quality Improvement of Hardware Verification and Synthesis Algorithms
… such as equivalence checking, model checking, Automatic Test Pattern Generation (ATPG), functional Bi-decomposition, and technology mapping need to keep pace with these challenges. In this thesis, we are concerned with improving the quality and performance of different EDA algorithms …
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High Quality Test Generation at the Register Transfer Level
… size has also lead to significant growth in testing effort required to verify the design. In order to cope with the required effort, the testing problem must be approached from several different design levels. In particular, exploiting the Register Transfer Level for test generation allows …
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Search-space Aware Learning Techniques for Unbounded Model Checking and Path Delay Testing
… two related problems in Design Verification and Testing: Unbounded Model Checking and Path Delay Fault Testing, that commonly suffer from extremely large memory requirements. We propose efficient representations and intelligent learning techniques that reason on the problem structure and take …
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Optimization, Testing and Design-for-Testability of Flow-Based Microfluidic Biochips
… be processed independently, simultaneously, and automatically on a coin-sized microfluidic platform. However, the increases in integration level introduce new challenges in the design optimization and the testing of these devices, which impede their further adoption and deployment.</p><p>This …
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Search State Extensibility based Learning Framework for Model Checking and Test Generation
… intensive design verification and manufacturing test phases in the product life-cycle of a digital system. On the contrary, time-to-market constraints require faster verification and test phases; otherwise it may result in a buggy design or a defective product. This trend in the semiconductor …