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Showing 1 to 13 of 13 for “"Asynchronous logic"”.

  1. Asynchronous logic automata

    … of information and the spatially concurrent, asynchronous nature of logic, scaling down in size and up in complexity becomes significantly easier. In particular, we introduce "asynchronous logic automata", which are a specialization of both asynchronous cellular automata and Petri nets, and …

    mit Repository record for Asynchronous logic automata (opens in a new tab)

  2. Matrix multiplication with Asynchronous Logic Automata

    … investigate an alternative type of architecture, Asynchronous Logic Automata, which I conclude has the potential to be easy to program in a parametric way and execute very dense, high-throughput computation at a lesser energy cost than that of today's supercomputers. This architecture aligns …

    mit Repository record for Matrix multiplication with Asynchronous Logic Automata (opens in a new tab)

  3. Superconducting Asynchronous Logic for Ultra-low Power High Performance Computing

    … a single chip. This thesis proposes a modular, asynchronous superconducting computing framework which aims to solve both of these problems. A discrete set of logic gates are proposed and implemented using Adiabatic Quantum Flux Parametron (AQFP) logic. AQFP logic devices can achieve picosecond …

    mit Repository record for Superconducting Asynchronous Logic for Ultra-low Power High Performance Computing (opens in a new tab)

  4. ALA ASIC : a standard cell library for Asynchronous Logic Automata

    … library with related tools and designs for Asynchronous Logic Automata (ALA) gates in a generic 90nm process development kit that allows a direct one-to-one mapping from software to hardware. Included are basic design tools to enable writing ALA software, the necessary hardware designs for …

    mit Repository record for ALA ASIC : a standard cell library for Asynchronous Logic Automata (opens in a new tab)

  5. Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic

    … By doing away with the constrains of a clock, asynchronous sequential circuit designs can achieve a much greater level of efficiency. The utilization of asynchronous logic synthesis flows has enabled researchers to better implement asynchronous circuit designs which have been optimized using …

    arkansas Repository record for Asynchronous Circuit Synthesis Using Multi-Threshold NULL Convention Logic (opens in a new tab)

  6. Asynchrobatic logic for low-power VLSI design

    In this work, Asynchrobatic Logic is presented. It is a novel low-power design style that combines the energy saving benefits of asynchronous logic and adiabatic logic to produce systems whose power dissipation is reduced in several different ways. The term “Asynchrobatic” is a new word that can be …

    westminster Repository record for Asynchrobatic logic for low-power VLSI design (opens in a new tab)

  7. Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits

    … of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL circuits in 3D IC. Several FIR filter designs …

    arkansas Repository record for Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits (opens in a new tab)

  8. Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection

    … mechanisms. Delay-insensitive asynchronous circuits inherently have promising potentials in mitigating the effects of radiation due to their delay insensitivity. This thesis proposes the use of two delay-insensitive asynchronous logic architectures to mitigate the effects of up …

    arkansas Repository record for Radiation-Hardened Delay-Insensitive Asynchronous Circuits for Multi-Bit SEU Mitigation and Data-Retaining SEL Protection (opens in a new tab)

  9. Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures

    <p>Delay-insensitive asynchronous circuits have been the target of a renewed research effort because of the advantages they offer over traditional synchronous circuits. Minimal timing analysis, inherent robustness against power-supply, temperature, and process variations, reduced energy …

    arkansas Repository record for Technology Mapping, Design for Testability, and Circuit Optimizations for NULL Convention Logic Based Architectures (opens in a new tab)

  10. Ultra-low Voltage Digital Circuits and Extreme Temperature Electronics Design

    … process, Schmitt-trigger gate design, and asynchronous logic at supply voltages lower than 100 millivolts. The second project describes construction of a sensor digital controller for the lunar environment. Parts of the digital controller are an asynchronous 8031 microprocessor that is …

    arkansas Repository record for Ultra-low Voltage Digital Circuits and Extreme Temperature Electronics Design (opens in a new tab)

  11. Circuit design for logic automata

    The Logic Automata model is a universal distributed computing structure which pushes parallelism to the bit-level extreme. This new model drastically differs from conventional computer architectures in that it exposes, rather than hides, the physics underlying the computation by accommodating data …

    mit Repository record for Circuit design for logic automata (opens in a new tab)

  12. Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security

    … dissertation presents two Null Convention Logic (NCL) applications of asynchronous logic circuit design in nanotechnology and cryptographic security. The first application is the Asynchronous Nanowire Reconfigurable Crossbar Architecture (ANRCA); the second one is an asynchronous S-Box …

    must-thes Repository record for Null Convention Logic applications of asynchronous design in nanotechnology and cryptographic security (opens in a new tab)

  13. Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche

    … will imply several design levels, as system and logic, and new approaches called Design For Manufacturability (DFM) and Design For Reliability. The purpose of the above approaches is to bring in the early design stages the awareness of the device reliability and manufacturability, in order to …

    bologna Repository record for Tecniche di progettazione tollerante alle variazioni per circuiti digitali in tecnologie nanometriche (opens in a new tab)