Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 16 of 16 for “"Architecture Memory"”.
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Performance analysis of machine learning applications on rapid: a highly parallel computer architecture
… of machine learning applications on different architectures. In this thesis, we evaluate the performance of six common machine learning algorithms: K-Means, K-Nearest Neighbors, Linear Regression, Latent Dirichlet Allocation, Deep Neural Network, and Radix Sort on RAPID. RAPID is a highly …
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Themes On A Fallow House
Themes on a Fallow House is a study of architecture and its effect on the way we create collective memories, accumulate material culture, and associate ourselves with place. Through experimenting with analog processes and materials, this work aims to suggest that architecture acts as a repository …
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A characteristic study of memory over the compute eXpress link
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01
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EMACS: efficient CXL-based memory access counters
Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2026-05-01
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Efficient memory access in modern accelerators
Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2024-05-01
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Memory and Intuition: An Uncovering of Sensibilities
This is an exploration beginning with memory of growing up in and exploring a forest surrounding my childhood home. This environment encompassed overwhelming scale and comforting intimacy, with a small intervention that related them. My thesis attempts to extract memory from growing up in the woods …
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Color reclamation for heap memory coloring scheme in PIPE tagged-memory architecture
Memory safety violations remain a significant hurdle as people try to secure computer software. The PIPE project proposed an approach to securing software by tagging memory and registers with color tags and defining policies in terms of the tags to disallow instructions violating memory safety. …
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Towards Using Free Memory to Improve Microarchitecture Performance
A computer system's memory is designed to accommodate the worst-case workloads with the highest memory requirement; as such, memory is underutilized when a system runs workloads with common-case memory requirements. Through a large-scale study of four production HPC systems, we find that memory …
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High Performance Architecture using Speculative Threads and Dynamic Memory Management Hardware
… have shifted from control flow Von-Neumann architecture back to dataflow architecture again in order to explore scalable architectures leading to multi-core systems with several hundreds of processing elements. In this dissertation, I address how the performance of modern processing systems …
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Cache design exploration in a general purpose massively parallel architecture
Memory model design is a major part of any modern processor architecture. There are many design choices and tradeoffs to be considered, and these often need to be tightly coupled to the processing unit's arcitecure. The increased popularity of massively parallel architectures has motivated …
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Prototyping Hardware-compressed Memory for Multi-tenant Systems
Software memory compression has been a common practice among operating systems. Since then, prior works have explored hardware memory compression to reduce the load on the CPU by offloading memory compression to hardware. However, prior works on hardware memory compression cannot provide critical …
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Efficient and Verifiable Timing Channel Protection for Multi-Core Processors
… attacks in the shared on-chip networks and memory controllers. We proposed multiple protection mechanisms for on-chip networks, caches and memory controllers. Our protection schemes cover three high-level approaches: bi-directional protections, uni-directional protections and protections …
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Flexible memory protection for multicore processors
A system’s memory access control mechanisms profoundly impact the performance, reliability, security, and composability of the software it runs. Desirable features of an access control mechanism include: the ability to grant arbitrary permissions on any region of memory to any thread in the system; …
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Memory Turbo Boost: Architectural Support for Using Unused Memory for Memory Replication to Boost Server Memory Performance
A significant portion of the memory in servers today is often unused. Our large-scale study of HPC systems finds that more than half of the total memory in active nodes running user jobs are unused for 88% of the time. Google and Azure Cloud studies also report unused memory accounts for 40% of the …
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Design and prototyping of Hardware-Accelerated Locality-aware Memory Compression
… the chip. This thesis describes the accelerator architecture, implementation, and prototype for one of such functions namely "Locality-Aware memory compression" which is part of the "OS-controlled memory compression" scheme that has been actively deployed in today's OSes. In brief, OS-controlled …
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Making non-volatile memory programmable
Byte-addressable, non-volatile memory (NVM) is emerging as a revolutionary memory technology that provides persistence, near-DRAM performance, and scalable capacity. By using NVM, applications can directly create and manipulate durable data in place without the need for serialization out to SSDs. …