Global ETD Search

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Showing 1 to 15 of 15 for “"Address translation"”.

  1. Impact of Network Address Translation on Router Performance

    Network Address Translation (NAT) is a method by which Internet Protocol (IP) addresses are translated from one group to another, in a manner transparent to the end users. It translates the source and destination addresses and ports in the Internet Protocol datagram. There are several benefits for …

    vt Repository record for Impact of Network Address Translation on Router Performance (opens in a new tab)

  2. Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors

    … of the silicon substrate. In this thesis, we address these challenges in a framework that targets correct execution and performance on three coordinates: 1) tolerating permanent faults, 2) facilitating static and dynamic verification through precise specifications, and 3) designing scalable …

    duke Repository record for Cost-effective Designs for Supporting Correct Execution and Scalable Performance in Many-core Processors (opens in a new tab)

  3. Design of Efficient Simple COMA Architectures

    Our address translation hardware is then used to improve on existing approaches for managing pages between S-COMA and CC-NUMA modes in hybrid systems.

    uiuc Repository record for Design of Efficient Simple COMA Architectures (opens in a new tab)

  4. Hardware Memory Compression for Large-scale Systems

    … (1) applications are more demanding on address translation, (2) many users execute workloads requesting different amounts of memory concurrently, and (3) these systems have stricter reliability requirements. These properties introduce new challenges when implementing hardware memory …

    vt Repository record for Hardware Memory Compression for Large-scale Systems (opens in a new tab)

  5. Live Library Upgrades via CRIU: A Novel Approach to Patch Security Vulnerabilities in Running Processes

    … The approach combines metadata edits, address translation, and memory dump rewriting. By patching file backed mappings and leveraging ELF internals, we inject the new library while the dynamic loader transparently re resolves references. A synthetic execution captures memory resident …

    uic

  6. NATRON : overlay routing to oblivious destinations

    … uses a combination of IP tunneling and network address translation to allow members of the overlay to communicate with hosts outside the overlay network via other overlay members. In order to estimate the potential performance improvement a system like NATRON might provide, we performed an …

    mit Repository record for NATRON : overlay routing to oblivious destinations (opens in a new tab)

  7. A software approach to accelerating memory translation for virtualized clouds

    Submission original under an indefinite embargo labeled 'Open Access'. The submission was exported from vireo on 2024-09-16 without embargo terms

    uiuc Repository record for A software approach to accelerating memory translation for virtualized clouds (opens in a new tab)

  8. Arm systems semantics

    … verification. However, the system semantics, of address translation and TLB maintenance, instruction-fetch and its required cache maintenance, and exceptions and interrupts, remains mostly obscure, leaving us without a solid foundation for verification of security-critical systems software. We …

    cambridge Repository record for Arm systems semantics (opens in a new tab)

  9. Enabling malware remediation in expanding home networks

    … and notification of compromise. However, Network Address Translation (NAT) and IPv6 Privacy Extensions prevent ISPs from identifying the specific compromised device. We refer to this lastmile extension of the IP traceback problem as the residential source identification problem. As the IoT grows, …

    mit Repository record for Enabling malware remediation in expanding home networks (opens in a new tab)

  10. Accelerating The Discontinuous Galerkin Cell-Vertex Scheme (Dg-Cvs) Solver On Cpu-Gpu Heterogeneous Systems

    … kernel occupancy. We developed optimizations to address these concerns. Our proposed optimizations include thread remapping to minimize thread divergence and register pressure reduction to increase kernel occupancy. Our experiment results show that Dg-Cvs on gpu outperforms cpu by up to 57\% …

    mississippi Repository record for Accelerating The Discontinuous Galerkin Cell-Vertex Scheme (Dg-Cvs) Solver On Cpu-Gpu Heterogeneous Systems (opens in a new tab)

  11. A Network Mobility Survey and Comparison with a Mobile IP Multiple Home Address Extension

    This thesis addresses the paucity of research on network mobility with a taxonomy and a quantitative comparison on a real test bed of existing and forthcoming network mobility solutions. Broadly, network mobility solutions can be divided into two broad categories, intra-domain and inter-domain …

    vt Repository record for A Network Mobility Survey and Comparison with a Mobile IP Multiple Home Address Extension (opens in a new tab)

  12. Frequent Inventory of Network Devices for Incident Response: A Data-driven Approach to Cybersecurity and Network Operations

    … institutions, strategies such as dynamic addressing and address translation become necessary. The proliferation of the Internet of Things (IoT) makes this identification task even more difficult. Loss of intellectual property, extortion, theft, and reputational damage are all significant …

    vt Repository record for Frequent Inventory of Network Devices for Incident Response: A Data-driven Approach to Cybersecurity and Network Operations (opens in a new tab)

  13. Using current uptime to improve failure detection in peer-to-peer networks

    … that can adapt to the limitations network address translation devices.

    birmingham Repository record for Using current uptime to improve failure detection in peer-to-peer networks (opens in a new tab)

  14. Efficient Virtual Cache Coherency for Multi-core Systems and Accelerators

    … individual components to perform virtual address accesses without having to include their own hardware for address translation and memory protection. This thesis presents such a protocol, together with tooling and hardware infrastructure that are developed in the process of creating it. …

    cambridge Repository record for Efficient Virtual Cache Coherency for Multi-core Systems and Accelerators (opens in a new tab)