Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 20 of 68 for “"65nm"”.
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YIELD IMPROVEMENT FOR AN ACTUAL 65NM PRODUCT
This report is regarding my industrial attachment at Chartered Semiconductor Manufacturing Ltd. Fab 7 Process Integration department from July 2008 to December 2008. Process integration (PI) is the synthesis of process control, process engineering and process modeling and simulation into tools that …
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Structural Design and Optimization of 65nm Cu/low-k Flipchip Package
This paper describes the optimization of the structural design of Charteredb s C65 nm 21 mm x 21 mm die size FCBGA package incorporated with fully active and functional 9-metal Cu/ low-k layers and 150um interconnect pitch. The low-k material used in this study is non-porous SiCOH with a k value of …
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Design and practical realization of polymorphic crosstalk circuits using 65nm TSMC PDK
… implementation of the crosstalk gates at 65nm. I will detail the steps that we have performed while designing the crosstalk circuits and their layouts, the challenges we faced while implementing the new circuit techniques using conventional design approaches and PDK, and their solutions, …
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Design port and optimization of a high-speed SAR ADC comparator from 65nm to 0.11[mu]M
… camera SAR ADC has been ported from its original 65nm process to a 0.11[mu]m process. Its design has been analyzed and performance presented here. Additionally, an alternative latch-only architecture for the comparator has been designed and analyzed. In 0.11[mu]m the three-stage comparator …
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RC relaxational oscillator with high supply rejection
… zero-voltage coefficient point. Fabricated in a 65nm CMOS process, the prototype 1.5MHz oscillator consumes 6μW from 1V supply and achieves better than ±50ppm/ ̊C and ±1500ppm/V temperature and voltage sensitivities, respectively.
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Fault tolerant, low voltage SRAM design
… and 5ns for error detection at 1.2V using 65nm CMOS. Compared to conventional iterative decoding scheme in which error correction takes more than 100 clock cycles for 128-bit word length, the analyzed decoder has a significant latency advantage. Meanwhile, compared to the look-up table …
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Ultra-dynamic voltage scalable (U-DVS) SRAM design considerations
… operation. A 64kbit SRAM has been designed in 65nm CMOS process and the fabricated chip has been tested, demonstrating operation at power supply levels from 0.25V to 1.2V. This is the largest operating voltage range reported in 65nm semiconductor technology node. Additionally, another low …
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Broadband mm-wave signal generation and amplification in CMOS using synthetic impedance
… circuits was analyzed and simulated on a TSMC 65nm bulk CMOS process.
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A zero-crossing based pipelined analog-to-digital converter with supply voltage scalibility
… (ADC) has been designed and is fabricated in a 65nm CMOS process. The highly digital implementation characteristic of the zero-crossing detection technique enables energy efficient operation and voltage scaling. Supply voltage scaling based on the required sampling frequency and resolution …
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Physically Unclonable Functions based on Voltage Divider Arrays of MOSFETs in Subthreshold Region of Operation
… is 0.0225. The circuits are designed in TSMC 65nm technology using Cadence software and the computations and interpretations is done using MATLAB.
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Circuits for time-domain signal processing
… used to reduce DCDL non-linearity. Fabricated in 65nm CMOS process, the prototype DTC achieves 1.65ps peak integral non-linearity (INL) while consuming 10.13mW at 100MHz carrier frequency. The achieved range and resolution are 5.31ns and 330fs, respectively, while the integrated jitter is only …
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High-Voltage Compliant, Electrode-Invariant Neural Stimulation Electronics Compatible with Low-Voltage, Bulk-CMOS Integration
… a stand-alone DVS circuit has been fabricated in 65nm bulk-CMOS, demonstrating the power-supplying and transient performance required by the proposed stimulator design. Another chip, featuring the entire integrated neural stimulator front-end, has also been designed in 65nm bulk-CMOS, with …
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High-performance reference frequency generation techniques
… the efficacy of the quadrupler. Fabricated in a 65nm CMOS process, the proposed clock multiplier occupies an active area of 0.16mm2 and achieves 366fsrms integrated jitter at 4.752GHz output frequency while consuming 6.5mW power from a 1.0V supply of which 1.5mW is consumed in the quadrupler. …
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The impact of technology scaling on integrated analogue CMOS RF front-ends for wireless applications
… Two LNAs have been implemented in a contemporary 65nm standard CMOS process technology for usage in a low-cost low-power mobile 2.5G GSM receiver front-end. The first LNA serves the GSM low bands whereas the second LNA serves the GSM high bands. The underlying LNA architecture, consisting of two …
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Circuit Techniques for Multiple and Wideband Beamforming
… Three different designs are implemented in TSMC 65nm RF CMOS to demonstrate different solutions. The design in this thesis have included major RF blocks in state-of-art wireless transceiver: RF receiver, local oscillator, and RF transmitter. First, a RF/analog FFT based four-channel four-beam …
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Synthesis constraint optimization for near-threshold voltage design
… options on openMSP430 microcontroller with TSMC 65nm technology library and suggest the optimal design points to the future IC designers. We find synthesizing the microcontroller with the minimum design constraint gives us the best performance and energy consumption. We also run Monte Carlo …
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Energy-aware system design using circuit reconfigurability with a focus on low-power SRAMs
… of a circuit. A test-chip is fabricated in a 65nm LP CMOS process and the energy monitoring circuit is demonstrated for an SRAM application. The small power (< 0.1%) and area overhead (16%) of the energy monitor motivated its usage within a system level application. Next, as a collaboration of …
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Generation of noise power at THz frequencies using CMOS schottky diodes in avalanche breakdown
… Two sets of test diodes manufactured in TSMC's 65nm CMOS process were characterized in order to determine the optimal diode design for generating noise power. Measurements show that shallow trench insulation separated (STI) schottky diodes have nearly ideal breakdown characteristics while …
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