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Showing 1 to 4 of 4 for “"3D integration technology"”.

  1. Designing High-Performance Microprocessors in 3-Dimensional Integration Technology

    … demonstration of the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of …

    gatech Repository record for Designing High-Performance Microprocessors in 3-Dimensional Integration Technology (opens in a new tab)

  2. ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits

    Recent developments in semiconductor processing technology has enabled the fabrication of a single integrated circuit (IC) with multiple device-interconnect layers or wafers stacked on each other. This approach is commonly referred to as the 3D integration of ICs. Although there has been …

    mit Repository record for ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits (opens in a new tab)

  3. In-Memory Computing Architecture for Deep Learning Acceleration

    … memory and logic devices, as well as advanced integration technologies. In the first work, I present the first training accelerator architecture, ReGAN, for unsupervised deep learning. ReGAN follows the process-in-memory strategy by leveraging energy efficiency of resistive memory arrays for …

    duke Repository record for In-Memory Computing Architecture for Deep Learning Acceleration (opens in a new tab)

  4. Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs

    … a large and complex system. In addition to NOCs, 3D integration technology using through-silicon-vias (TSVs) can also alleviate the problems caused by long global interconnects and it offers more innovative design choices compared to traditional 2D integrated circuits (ICs).</p><p>Regardless of …

    duke Repository record for Optimization of Test and Design-for-Testability Solutions for Many-Core System-on-Chip Designs (opens in a new tab)