Global ETD Search
Search theses and dissertations gathered from participating repositories worldwide. Every result links back to the library that holds it. No account is needed.
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Showing 1 to 14 of 14 for “"3D Integrated Circuits"”.
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Design for pre-bond testability in 3D integrated circuits
… we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. …
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Interconnect design techniques for multicore and 3D Integrated circuits.
… and wire dimensions. Three dimensional (3D) circuit technology, with multiple tiers of active devices stacked above each other, is a key approach to achieve increasing levels of integration and performance in the future. Concomitant with exponentially reducing device dimensions, designers …
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Graphene Nanotechnology the Next Generation Logic, Memory and 3D Integrated Circuits
… the metal-MoS2 contact. The three dimensional integrated circuit (3D- IC) is expected to extend Moore's law. To reduce interconnects and time delay, semiconductor industry is shifting 2D-IC to 2.5D-IC and 3D-IC. 3D-IC is the ultimate goal of the semiconductor industry, where 2.5D-IC is an …
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Commercialization of low temperature copper thermocompression bonding for 3D integrated circuits
… technology for realization of three-dimensional integrated circuits (3DIC) with reduced interconnect delay and correspondingly increased circuit speed and decreased power dissipation, along with an improved form factor and portability. One of the most recent novel and promising wafer bonding …
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ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS
… the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor …
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ERNI-3D : a technology-generic tool for interconnect reliability projections in 3D integrated circuits
… has enabled the fabrication of a single integrated circuit (IC) with multiple device-interconnect layers or wafers stacked on each other. This approach is commonly referred to as the 3D integration of ICs. Although there has been significant research on the impact of 3D integration on …
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ADVANCED MATERIALS DEVELOPMENT AND MANUFACTURING - DEVELOPMENT OF THERMALLY STABLE THIN FILMS WITH HIGH STRESS TUNABILITY
… the semiconductor industry is heading towards 3D integrated circuits by stacking die or NAND cells vertically. The higher number of film deposition from NAND cell stacking result in higher compressive wafer bow of Production Silicon Wafers which is undesirable in manufacturing process flow due …
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Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs
A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack …
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A multi-process reactor for thin film transistor fabrication at low temperatures
… flat panel displays, large area electronics and 3D integrated circuits. This thesis describes advances made in the technology for the fabrication of TFT's. A Multi-Process reactor has been designed to produce device quality layers on Coming 1733 glass substrates, which are incompatible with …
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Predictive transient circuit simulations of charged device model ESD events in system in package chips
… the voltage stress experienced by the devices on integrated circuit components stressed by the charged device model (CDM) electro-static discharge (ESD) testers. The thesis presents a simple package modeling methodology that can be used to create a distributed model to simulate the voltage stress …
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Designing High-Performance Microprocessors in 3-Dimensional Integration Technology
… the impact of a new emerging technology called 3D-integration technology on conventional high-performance microprocessors. 3D-integration technology stacks active devices in the vertical dimension in addition to the conventional horizontal dimension. The additional degree of connectivity in the …
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Characterization of bonded copper interconnects for three-dimensional integrated circuits
… industry is demanding ultra large-scale integrated (ULSI) circuits with increasing performance at minimum cost and power dissipation. As the critical dimensions in ULSI design continue to shrink, system performance of integrated circuits will be increasingly dominated by interconnect …
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Performance variations due to layout-dependent stress in VLSI circuits
… layout optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor …