Global ETD Search
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Showing 1 to 17 of 17 for “"3D ICs"”.
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Hybrid microfluidic cooling and thermal isolation technologies for 3D ICs
A key challenge for three dimensional (3D) integrated circuits (ICs) is thermal management. There are two main thermal challenges in typical 3D ICs. First, in the homogeneous integration with multiple high-power tiers, an effective cooling solution that scales with the number of dice in the stack …
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Stability analysis for SRAM cells with TSV induced stress in 3D ICs
Three-dimensional integrated circuits (3D-IC) have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs while also helping to reduce wire delay and increase memory throughput. While this technology offers many potential advantages, it also produces …
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Electro-Thermal Codesign in Liquid Cooled 3D ICs: Pushing the Power-Performance Limits
… due to advanced multi-core architectures and 3D integration technologies. Nowadays the problems of increased chip power density, leakage power and system temperatures have become major obstacles for further improvement in chip performance. The conventional air cooling based heat sink has been …
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Placement for fast and reliable through-silicon-via (TSV) based 3D-IC layouts
… found in three-dimensional integrated circuits (3D ICs) that use through-silicon vias (TSVs) at placement stage. Four main works that support this goal are included. In the first work, wirelength of TSV-based 3D ICs is the main focus. In the second work, stress-induced carrier mobility variation …
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Asynchronous 3D (Async3D): Design Methodology and Analysis of 3D Asynchronous Circuits
… dissertation focuses on the application of 3D integrated circuit (IC) technology on asynchronous logic paradigms, mainly NULL Convention Logic (NCL) and Multi-Threshold NCL (MTNCL). It presents the Async3D tool flow and library for NCL and MTNCL 3D ICs. It also analyzes NCL and MTNCL …
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ELECTRONIC DESIGN AUTOMATION TOOLS AND DESIGN STUDY FOR HETEROGENEOUS MONOLITHIC 3D INTEGRATED CIRCUITS
… the transistor performance, Three Dimensional (3D) Integrated Circuit (IC) Design, which is the focus of this work, is another promising alternative for going beyond Moore’s Law. 3D IC provides power, performance, and area (PPA) benefits at full-chip level, orthogonal to the transistor …
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Thermal designs, models and optimization for three-dimensional integrated circuits
Three-dimensional integrated circuits (3D ICs), a novel packaging technology, are heavily studied to enable improved performance with denser packaging and reduced interconnects. Despite numerous advantages, thermal management is the biggest bottleneck to expanding the applications of this device …
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Design for pre-bond testability in 3D integrated circuits
… we propose several DFT techniques specific to 3D stacked IC systems. The goal has explicitly been to create techniques that integrate easily with existing IC test systems. Specifically, this means utilizing scan- and wrapper-based techniques, two foundations of the digital IC test industry. …
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Design and Study of an Electron Beam System for Silicon Recrystallization
… of Three-Dimensional Integrated Circuits (3D-ICs) is a key advancement in semiconductor technology. Technologies like Silicon-On-Insulator (SOI) can be used for the individual layers of a 3D-IC. 3D-ICs offer the potential to create more compact and powerful devices, which can be beneficial …
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Performance variations due to layout-dependent stress in VLSI circuits
… layout optimization strategies are derived. In 3D-ICs, through silicon vias (TSVs) introduce unintentional thermally-induced stress in the layout, which results in placement dependent circuit performance variations. Thermal-stress effects are coupled with other temperature effects on transistor …
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DENSE 3D HETEROGENEOUS INTEGRATION USING SELECTIVE COBALT ALD DEPOSITION AND RECONSTITUTED TIERS
… three-layered structure, which emulates 3D ICs stacking, is fabricated and carefully characterized. The testbed shows seamless Co interconnection between the Cu pads after Co ALD deposition for 1000 cycles. The electrical measurements demonstrate over 90% yield, which prove the Co …
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Laser Crystallization of Silicon Thin Films for Three-Dimensional Integrated Circuits
The three-dimensional integration of microelectronics is a standard that has been actively pursued by numerous researchers in a variety of technical ways over the years. The primary aim of three-dimensional integration is to alleviate the well-known issues associated with device shrinking in …
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On-Chip Isotropic Microchannels for Cooling Three Dimensional Microprocessors
… reactive ion etching (DRIE) process for cooling 3D ICs. Three dimensionally independent microchannels are fabricated by utilizing the RIE lag effect. This allows complex microchannel configurations to be fabricated using a single mask and single silicon etch step. Furthermore, the microchannels …
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3D modeling and integration of current and future interconnect technologies
… the calculated results are within 10% of Ansys Q3D extracted values. Through silicon via (TSV) is one of the key components of the emerging 3D ICs. However, increasing number of TSVs in smaller silicon area leads to some severe negative impacts on the performance of the 3D IC. Growing signal …
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Methods for nano-precise overlay in advanced in pick-and-place assembly
… of new nanofabrication applications, including 3D ICs and secure super-sized SoCs, by enabling nano-precise assembly of pre-fabricated device blocks (PFBs). N-MAP incorporates a vacuum-based superstrate (in place of the template in J-FIL), which is designed to pick up PFBs and to place them at …
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A Design for Test and Security Methodology for Integrated Circuits
… attackers of layout resources to route HTs. 3D full-wave EM field simulations using High-Frequency Structural Simulator (HFSS) show that tampering with a chip to insert a Trojan of 12 μm2, the area required to insert an inverter, can be detected through the magnetic signature. Some unique HTs …
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs
<p>As integrated circuits (ICs) continue to scale to smaller dimensions, long interconnects</p><p>have become the dominant contributor to circuit delay and a significant component of</p><p>power consumption. In order to reduce the length of these interconnects, 3D integration</p><p>and 3D stacked …