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Virginia Tech

In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs

Abstract

dc:description.abstract

FPGA fault recovery techniques, such as bitstream scrubbing, are only limited to detecting and correcting soft errors that corrupt the configuration memory. Scrubbing and related techniques cannot detect permanent faults within the FPGA fabric, such as short circuits and open circuits in FPGA transistors that arise from electromigration effects. Several Built-In Self-Test (BIST) techniques have been proposed in the past to detect and isolate such faults. These techniques suffer from routing congestion problems in modern FPGAs that have a large number of logic blocks. This thesis presents an improved BIST architecture for all Xilinx 7-Series FPGAs that is scalable to large arrays. The two primary sources of overhead associated with FPGA BIST, the test time and the memory required for storing the BIST configurations, are also reduced when compared to previous FPGA-BIST approaches. The BIST techniques presented here also eliminate the need for using any of the user I/O pins, such as a clock, a reset, and test observation pins; therefore, it is suitable for immediate deployment on any system with Xilinx 7-Series FPGAs. With faults detected, isolated, and corrected, the effective MTBF of a system can be extended.

Degree

thesis:*
Name thesis:degree_name
Master of Science
Level thesis:degree_level
masters
Discipline thesis:degree_discipline
Computer Engineering
Department dc:contributor.department
Electrical and Computer Engineering
Grantor dc:publisher
Virginia Tech
Year dc:date.issued
2015

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Modi, Harmish Rajeshkumar
Chair dc:contributor.committeechair
  • Athanas, Peter M.
Committee members dc:contributor.committeemember
  • Dietrich, Carl B.
  • Hsiao, Michael S.

Subjects

dc:subject × 3

Rights

dc:rights
Statement dc:rights
  • In Copyright

Identifiers

dc:identifier.*
Dc Identifier Other
vt_gsexam:6058
OAI identifier oai:identifier
oai:vtechworks.lib.vt.edu:10919/55123

Chain of custody

source
Harvested from
Virginia Tech
Base URL
vtechworks.lib.vt.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Modi, Harmish Rajeshkumar. In-System Testing of Configurable Logic Blocks in Xilinx 7-Series FPGAs. masters thesis, Virginia Tech, 2015. http://hdl.handle.net/10919/55123