An efficient test generation algorithm for behavioral descriptions of digital devices

An efficient test generation algorithm for behavioral descriptions is discussed. It generates tests for behavioral dataflow descriptions of digital circuits written in VHDL. The algorithm accepts input descriptions containing multiple process statements and concurrent signal assignment statements. The fault model based on previous research includes micro-operation and control faults. The test generation algorithm uses artificial intelligence techniques of goal trees and rule databases and it can make use of human understanding of the device model to generate more efficient tests. An improved timing model helps detect conflicts more quickly and improves the speed performance of the algorithm. The test generation algorithm has been used to generate tests for complex circuits. Results of fault coverage experiments for some of these circuits is presented.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Polytechnic Institute and State University

Year dc:date.issued

1988

Author dc:creator

• Jani, Dhanendra Dinesh

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/10919/53723

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/53723