Abstract
dc:description.abstractUse of traditional gate level test generation techniques is prohibitively expensive and time consuming for VLSI chips. High level approaches to test generation have been proposed to improve the efficiency of test generation, e.g., the Behavioral Test Generator developed at Virginia Tech generates test vectors from high level Behavioral VHDL descriptions. To validate the utility of these test vectors, it needs to be established that they provide adequate coverage at the gate level. This thesis shows that test vectors obtained from the Behavioral Test Generator provide adequate coverage for the equivalent gate level circuit. A system that was developed to effectively evaluate the test vectors is presented. The implementation of Heuristic Test Generator to improve the coverage of the Behavioral Test Generator is explained.
Degree
thesis:*- Name thesis:degree_name
- Master of Science
- Level thesis:degree_level
- masters
- Discipline thesis:degree_discipline
- Electrical Engineering
- Department dc:contributor.department
- Electrical Engineering
- Grantor dc:publisher
- Virginia Tech
- Year dc:date.issued
- 1993
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Baweja, Gunjeetsingh
- Chair dc:contributor.committeechair
-
- Armstrong, James R.
- Committee members dc:contributor.committeemember
-
- Cyre, Walling R.
- Gray, Festus Gail
Rights
dc:rights- Statement dc:rights
-
- In Copyright
- Licence dc:rights.uri
- Language dc:language.iso
- en
Identifiers
dc:identifier.*- Dc Identifier Other
- etd-11102009-020104
- OAI identifier oai:identifier
- oai:vtechworks.lib.vt.edu:10919/45598