Optimizations for acyclic dataflow graphs for hardware-software codesign

Most computationally-intensive programs spend a majority of their time within a small portion of the executable code. A novel computer architecture and compiler, called PRISM-2, is introduced, which improves the performance of these programs by synthesizing the "most often" executed instructions. This is accomplished by augmenting a general-purpose processor with an array of FPGAs. The information regarding the structures to be synthesized is extracted from the high-level language (HLL) specification presented at the input of the PRISM-2 compiler. This behavioral specification is transformed into an internal, dataflow graph (DFG) format. Linear and loop optimizations are then performed to optimize this representation. Linear optimizations are the main topic of discussion in this thesis. The optimized DFG is then synthesized on the reconfigurable platform.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1994

Author dc:creator

• Motiwala, Quaeed

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-06302009-040504

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/43510