On the generation of test patterns for combinational circuits

In this thesis, methods of identification of redundant faults and test pattern compaction are presented. The aim of the research is to improve an existing test pattern generator ATALANTA by incorporating methods for identification of redundant faults and test compaction. The faults are modeled as stuck-at faults for combinational circuits. To guarantee the completeness of the generated test set all redundant faults should be identified. For this purpose, the process of dynamic unique sensitization is implemented. This process studies the circuit for the existing state of value assignments and determines the dynamic dominators to identify redundant faults. The test set size is compacted to reduce the test storage space and test application time. The process of compaction is done by shuffling the test set and simulating the re-arranged test set to drop unnecessary test patterns. Experimental results show that the methods lead to a smaller test set size and identification of all redundant faults.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical Engineering

Department dc:contributor.department

Electrical Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

1993

Author dc:creator

• Thakar, Sarita

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Language dc:language.iso

en

Dc Identifier Other

etd-04072009-040517

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/41915