Image Wavelet Compression Implementation Using a Run-Time Reconfigurable Custom Computing Machine

This thesis presents the design and implementation of the Image Wavelet Compression (IWC) algorithm on Field Programmable Gate Arrays (FPGAs) by using the run-time reconfigurable custom computing machine design tool Janus. The four routines implementing the IWC are discussed. The structure of Janus is introduced and the IWC implementation design framework to use Janus structure is described in detail. The Janus hardware circuit design model, which has been used in the IWC implementation, is demonstrated here. The hardware implementation results are presented and analyzed, focusing on reconfiguration and computing time. Future research areas are suggested to improve the Janus tool.

Name thesis:degree_name

Master of Science

Level thesis:degree_level

masters

Discipline thesis:degree_discipline

Electrical and Computer Engineering

Department dc:contributor.department

Electrical and Computer Engineering

Grantor dc:publisher

Virginia Tech

Year dc:date.issued

2000

Author dc:creator

• Ding, Zhimei

Chair dc:contributor.committeechair

• Athanas, Peter M.

Committee members dc:contributor.committeemember

• Midkiff, Scott F.
• Jones, Mark T.

• FPGA RTRC CCM

Statement dc:rights

• In Copyright

Licence dc:rights.uri

• http://rightsstatements.org/vocab/InC/1.0/

Dc Identifier Other

etd-07222000-13030026

OAI identifier oai:identifier

oai:vtechworks.lib.vt.edu:10919/34105