Advanced techniques for fast timing simulation of MOS VLSI circuits

The basic goals of the research presented in this thesis are to remove various shortcomings in existing fast timing simulators and to extend the scope and applicability of fast timing simulation to submicron digital circuits. Existing fast timing simulators have been shown to be extremely efficient in simulating large digital circuits compared to classical electrical-level simulators. However, these simulators have a number of accuracy-related problems: inaccurate MOS modeling, inadequate consideration of the effects of internal nodes in complex logic gates and of interconnect loading, etc. The thrust of this dissertation is in the investigation of techniques that will allow us to remove these shortcomings while preserving, as much as possible, the simulation efficiency.

Name thesis:degree_name

Ph.D.

Level thesis:degree_level

Dissertation

Discipline thesis:degree_discipline

Electrical Engineering

Grantor

University of Illinois at Urbana-Champaign

Year dc:date

2011

Author dc:creator

• Dharchoudhury, Abhijit

Contributors dc:contributor

• Kang, Sung Mo

• Engineering, Electronics and Electrical

Statement dc:rights

• Copyright 1995 Dharchoudhury, Abhijit

Language dc:language

eng

Identifier

AAI9543569
(UMI)AAI9543569

OAI identifier oai:identifier

oai:www.ideals.illinois.edu:2142/19213