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Purdue University

Power-efficient high-speed interface circuit techniques

Abstract

dc:description.abstract

<p>Inter- and intra-chip connections have become the new challenge to enable the scaling of computing systems, ranging from mobile devices to high-end servers. Demand for aggregate I/O bandwidth has been driven by applications including high-speed ethernet, backplane micro-servers, memory, graphics, chip-to-chip and network onchip. I/O circuitry is becoming the major power consumer in SoC processors and memories as the increasing bandwidth demands larger per-pin data rate or larger I/O pin count per component. The aggregate I/O bandwidth has approximately doubled every three to four years across a diverse range of standards in different applications. However, in order to keep pace with these standards enabled in part by process-technology scaling, we will require more than just device scaling in the near future. New energy-efficient circuit techniques must be proposed to enable the next generations of handheld and high-performance computers, given the thermal and system-power limits they start facing. ^ In this work, we are proposing circuit architectures that improve energy efficiency without decreasing speed performance for the most power hungry circuits in high speed interfaces. By the introduction of a new kind of logic operators in CMOS, called implication operators, we implemented a new family of high-speed frequency dividers/prescalers with reduced footprint and power consumption. New techniques and circuits for clock distribution, for pre-emphasis and for driver at the transmitter side of the I/O circuitry have been proposed and implemented. At the receiver side, new DFE architecture and CDR have been proposed and have been proven experimentally.</p>

Degree

thesis:*
Name thesis:degree_name
Doctor of Philosophy (PhD)
Level thesis:degree_level
Dissertation
Discipline thesis:degree_discipline
Electrical and Computer Engineering
Year
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Roa Fuentes, Elkim Felipe
Contributors dc:contributor
  • Byunhoo Jung
  • Byunghoo Jung
  • Anand Raghunathan
  • Kaushik Roy
  • William J. Chappell

Subjects

dc:subject × 2

Identifiers

dc:identifier.*
OAI identifier oai:identifier
oai:docs.lib.purdue.edu:open_access_dissertations-1494

Chain of custody

source
Harvested from
Purdue University
Base URL
docs.lib.purdue.edu/do/oai/
Last updated
2026-07-24
Source record
OAI-PMH GetRecord
citation

Roa Fuentes, Elkim Felipe. Power-efficient high-speed interface circuit techniques. Dissertation thesis, 2014. https://docs.lib.purdue.edu/open_access_dissertations/351