Use of competitive benchmarking information to improve equipment utilization and throughput in a semiconductor manufacturing system

The use of contract manufacturers is becoming more common in the semiconductor industry. These foundries. as they are known in the industry, focus their efforts on achieving operational excellence in order to manufacture semiconductor products more cost effectively than their customers can internally. Intel has started using Foundries for non-microprocessor products in order to help them reserve internal production capacity for their microprocessors. A side benefit of the outsourcing process for Intel, is the opportunity to benchmark their own operational efficiency against that of their supplier. This thesis will discuss the process used for this benchmark study, its results and managerial implications of the findings. A benchmarking problem statement was defined including a rationale for focussing on the lithography area as the highest leverage point in the operation, and a description of the wafer throughput metric that was used for the comparison. The raw results of this study show a 33% deficit for Intel compared with Supplier X in lithography throughput. These data, however, included effects of both different machine type!i and different operational practices. Because Intel has strategic reasons for selecting its equipment vendors, the focus of this study was not to suggest that they switch lithography equipment vendors. Rather, the goal was to understand how much of this deficit could be attributed to Supplier X's superior operational practices. In order to remove the convolving effects of different equipment run rates, a set of experiments was performed to separate machine effects from operational effects allowing for a direct comparison operational efficiencies. These experiments showed that Intel has a 15% deficit in lithography throughput when compared with Supplier X, after normalizing for equipment effects. Reasons for this deficit could include Intel's excessive use of testing procedures, Intel's risk averse operational culture and Intel's possible managerial hubris.

Department dc:contributor.department

Massachusetts Institute of Technology. Department of Mechanical Engineering

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

1999

Author dc:creator

• Bhatia, Manish Hasso

Advisor dc:contributor.advisor

• Jung-Hoon Chun and Robert S. Gibbons.

• Sloan School of Management
• Mechanical Engineering

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/9743

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/9743