Back to search

Massachusetts Institute of Technology

Use of high-level design information for enabling automation of fine-grained power gating

Abstract

dc:description.abstract

Leakage power reduction through power gating requires considerable design and verification effort. Conventionally, extensive analysis is required for dividing a heterogeneous design into power domains and generating control signals for power switches because of the need to preserve design behavior. In this thesis, I present a scheme which uses high-level design description to automatically generate a collection of fine-grain power domains and associated control signals. For this purpose, we explore the field of high-level design languages and select rule-based languages on Quality-of- Result metrics. We provide algorithms to enable automatic power domain partitioning in designs generated using rule-based languages. We also describe techniques for collecting the dynamic activity characteristics of a domain, viz. total inactivity and frequency of inactive-active transitions. These metrics are necessary to decide the generated domains' viability for power gating after accounting for energy loss due to transitions. Our automated power gating technique provides power savings without exacerbating the verification problem because the power domains are correct by construction. We illustrate our technique using various test-cases: two wireless decoder designs, a million-point sparse FFT design and a RISC processor design.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Electrical Engineering and Computer Science.
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2014

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Agarwal, Abhinav
Advisor dc:contributor.advisor
  • Arvind.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/93051
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/93051

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Agarwal, Abhinav. Use of high-level design information for enabling automation of fine-grained power gating. Massachusetts Institute of Technology, 2014. http://hdl.handle.net/1721.1/93051