Minimizing the risk qualification test wafers have on the manufacturing readings of a new microprocessor fabrication site through data processes

Thesis (S.M.)--Massachusetts Institute of Technology, Sloan School of Management; and, (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2001.

Department dc:contributor.department

Sloan School of Management.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2001

Author dc:creator

• Howe, Jonathan E. (Jonathan Emerson), 1973-

Advisor dc:contributor.advisor

• Stephen C. Graves and Stanley B. Gershwin.

• Sloan School of Management.
• Mechanical Engineering.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/84226

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/84226