Micro-architectural analysis of SPACERAM processing element

SPACERAM is a SIMD architecture optimized for symbolic spatial computations implemented with multiple banks of DRAM combined with an array of processing elements. Such an architecture facilitates very high processor-memory bandwidth and hence allows for applications requiring orders of magnitude higher processing and update rates per DRAM than any current hardware. The array of processing elements process data coming simultaneously from several memory blocks by applying appropriate shifting and lookup table updates to them. Every processing element contains a permuter which makes it possible to assign data bits from any DRAM block to any functional block within the processing element as specified by controller setup. The lookup table is implemented as a common bus shared by all the processing elements. Micro-architectural analysis of such a processing element presents various possible implementations and trade-off issues associated with them.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

1998

Author dc:creator

• Pant, Amrit R. (Amrit Raj), 1971-

Advisor dc:contributor.advisor

• Thomas F. Knight, Jr.

• Electrical Engineering and Computer Science

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/47717

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/47717