A low power high power supply rejection ratio bandgap reference for portable applications

A multistage bandgap circuit with very high power supply rejection ratio was designed and simulated. The key features of this bandgap include multiple power modes, low power consumption and a novel resistor trimming strategy. This design was completed in deep submicron CMOS technology, and is especially suited for portable applications. The bandgap designed achieves over 90 dB of power supply rejection and less than 17 microvolts of noise without any external filtering. With an external filtering capacitor, this performance is significantly enhanced. In addition, the design includes an efficient voltage-to-current converter and a fast-charge circuit for charging the external capacitor.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Sundar, Siddharth

Advisor dc:contributor.advisor

• Eric Kimball and Michael Perrott.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/46517

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/46517