An exploratory design of a 65 nm CMOS buck converter for maximum efficiency

Portable battery-operated consumer devices, such as mp3 players, cell phones, and digital cameras, are becoming ever more prevalent and so the need for long battery life is increasingly important. These small devices contain power converters that produce lower supply voltages from the fixed battery voltage source. For long battery life, it is necessary to maximize the efficiency of the power converter. A design is proposed for the topology and control of a 65 nm CMOS DC/DC switch-mode converter converting a 3 V battery supply to a 1.2 V output voltage for a maximum output current of 100 mA. The goal of the project was to maximize converter efficiency and improve on the maximum 40% efficiency of a traditional linear regulator. With the proposed topology and control scheme described in this report, the buck converter operates at a switching frequency of 10 to 75 MHz with a maximum efficiency of 93.63%.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Lin, Doris, M. Eng. Massachusetts Institute of Technology

Advisor dc:contributor.advisor

• David J. Perreault.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/46024

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/46024