Substrate engineering for monolithic integration of III-V semiconductors with Si CMOS technology

Ge virtual substrates, fabricated using Si1-xGex-.Ge, compositionally graded buffers, enable the epitaxial growth of device-quality GaAs on Si substrates, but monolithic integration of III-V semiconductors with Si CMOS using this platform is hampered by the large thickness of the Si1-xGex graded region. To address this issue, the Silicon on Lattice-engineered Silicon (SOLES) was developed, consisting of a silicon-on-insulator (SOI) structure fabricated on a Ge virtual substrate. Placement of the Si device layer at the surface makes it possible to process this platform similarly to typical SOI wafers, with the added functionality of a buried III-V template which can be used for GaAs device fabrication. This platform was fabricated using a scalable layer transfer technique. AlInGaP LEDs were also demonstrated on a SOLES substrate. In addition, an alternative growth process was investigated for Si1-xGex virtual substrates with lower threading dislocation density (TDD) and thickness. This process, the thermally relaxed ultra-thin (TRUT) buffer process, consists of coherent growth of lattice-mismatched Si1.xGex layers, followed by post-growth annealing. Growth of TRUT buffers over the Si0.5Ge0.5 to Si0.3Ge0.7 alloy range with high strain levels resulted in the nucleation of surface defects which appear to limit the maximum strain rate of compositionally graded buffers. However, application of the TRUT process in the Si0.1Ge0.9 to Ge alloy range resulted in relaxed Ge virtual substrates with a 59% reduction in TDD compared to conventional processes. Lastly, growth of high-quality lattice-matched GaAsyP1.y on Si0.5Ge0.5, Si0.3Geo.7, and Si0.2Ge0.8 virtual substrates was investigated.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Materials Science and Engineering.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2008

Author dc:creator

• Dohrman, Carl Lawrence

Advisor dc:contributor.advisor

• Eugene A. Fitzgerald.

• Materials Science and Engineering.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

eng

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/44323

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/44323