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Massachusetts Institute of Technology

Substrate and channel engineering for improving performance of strained-SiGe MOSFETs

Abstract

dc:description.abstract

With VLSI technology moving closer towards fundamental physical limits, a way to further improve the transistor drive current for superior circuit performance is enhancing the average velocity of carriers in the channel. In order to enable technology boosters like strained channels on the commercially developed Si platform, a low threading dislocation density SiGe platform is required. A relaxed SilGe. graded buffer creates a larger lattice constant on a Si substrate while providing low threading dislocation densities (TDD) on the order of 105 cm-2. For many III-V devices on Si, such as high-efficiency multi-junction solar cells, the SiGe graded buffer approach is hindered somewhat by the fact that relatively thick buffers must be grown to relieve the strain effectively. A way to reduce the thickness of SiGe graded buffer is to use larger mismatch (10% Ge difference) at each step. Growing a larger mismatch layer at high temperature leads to a higher threading dislocation density (TDD). In this work, the rate of plastic strain relaxation in a mismatched layer and misfit dislocation distribution in the layer are identified to be important parameters which affect the TDD in a mismatched SiGe layer.

Degree

thesis:*
Department dc:contributor.department
Massachusetts Institute of Technology. Department of Materials Science and Engineering
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2006

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Gupta, Saurabh, Ph. D. Massachusetts Institute of Technology
Advisor dc:contributor.advisor
  • Eugene A. Fitzgerald.

Subjects

dc:subject × 1

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/36200
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/36200

Chain of custody

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Harvested from
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Base URL
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Last updated
2026-07-22
Source record
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citation

Gupta, Saurabh, Ph. D. Massachusetts Institute of Technology. Substrate and channel engineering for improving performance of strained-SiGe MOSFETs. Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36200