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Massachusetts Institute of Technology
Optimization of power and delay in VLSI circuits using transistor sizing and input ordering
Abstract
dc:descriptionThesis (M.S.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1994.
Degree
thesis:*- Department dc:contributor.department
- Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science
- Grantor dc:publisher
- Massachusetts Institute of Technology
- Year dc:date.issued
- 1994
Author and committee
dc:creator, dc:contributor.*- Author dc:creator
-
- Tan, Chin Hwee
- Advisor dc:contributor.advisor
-
- Jonathan Allen.
Subjects
dc:subject × 1Rights
dc:rights- Statement dc:rights
-
- M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
- Licence dc:rights.uri
- Language dc:language.iso
- eng
Identifiers
dc:identifier.*- Handle dc:identifier.uri
- http://hdl.handle.net/1721.1/35979
- OAI identifier oai:identifier
- oai:dspace.mit.edu:1721.1/35979