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Massachusetts Institute of Technology

Optimization of in-line semiconductor measurement rates : balancing cost and risk in a high mix, low volume environment

Abstract

dc:description.abstract

Due to a number of market development over the last decade, semiconductor manufacturing companies, including Intel Corporation, have added significant numbers of primarily high growth rate, high-mix, low-volume (HMLV) products to their portfolios. The rapid transition from high-volume manufacturing (HVM) to HMLV manufacturing has caused significant problems. Foremost, the needs of many HMLV customers are different from HVM customers and require different operational tradeoffs. Moreover, many of the HVM focused metrics, tools, systems and processes have proven ill-suited for managing the added complexities and more varied needs of HMLV customers. This thesis examines many of the problems caused by introducing HMLV products into an HVM wafer fabrication facility (commonly referred to as a fab), and explores potential solutions such as improved cultural and organizational alignment; capacity management and setup elimination; and scheduling and work-in-process management to name a few. Although the discussion focuses on semiconductor operations, the concepts easily generalize to other companies struggling with achieving operational excellence (OpX) in an HMLV environment. In addition to exploring the macroscopic HMLV issues, we also feature an in-depth analysis of one aspect of achieving OpX in the HMLV environment: the optimization of in-line metrology skip rates. Based on a review of the current methods, a new approach is suggested based on a Bayesian economic skip-lot model we call MOST/2. In general, MOST/2 suggests that significant cost savings can be realized with only modest increases in the material at risk per excursion if measurement rates are further reduced. Compared with the other methods analyzed, the data indicates that MOST/2

Degree

thesis:*
Department dc:contributor.department
Leaders for Manufacturing Program at MIT
Grantor dc:publisher
Massachusetts Institute of Technology
Year dc:date.issued
2004

Author and committee

dc:creator, dc:contributor.*
Author dc:creator
  • Pandolfo, Christopher R. (Christopher Robert), 1975-
Advisor dc:contributor.advisor
  • Roy E. Welsch and Duane Boning.

Subjects

dc:subject × 3

Rights

dc:rights
Statement dc:rights
  • M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.
Language dc:language.iso
eng

Identifiers

dc:identifier.*
Handle dc:identifier.uri
http://hdl.handle.net/1721.1/34770
OAI identifier oai:identifier
oai:dspace.mit.edu:1721.1/34770

Chain of custody

source
Harvested from
MIT
Base URL
dspace.mit.edu/oai/request
Last updated
2026-07-22
Source record
OAI-PMH GetRecord
citation

Pandolfo, Christopher R. (Christopher Robert), 1975-. Optimization of in-line semiconductor measurement rates : balancing cost and risk in a high mix, low volume environment. Massachusetts Institute of Technology, 2004. http://hdl.handle.net/1721.1/34770