Allocating decoupling capacitors to reduce simultaneous switching noise on chips

L dI/dt noise due to simultaneous switching of circuits on chips is a growing problem in VLSI design. This kind of noise can lead to timing errors and significant circuit slowdowns, if not kept within reasonable bounds. The most common way of reducing this form of noise is the addition of decoupling capacitance on chip. However, adding decoupling capacitance can take significant area and can make routing very difficult. The goals of this thesis are twofold: first, to characterize the relationship between noise propagation on chip and parameters such as on-chip resistance and capacitance; and second, to develop an algorithm which will minimize the number of decoupling capacitors on chip while simultaneously reducing the noise to within acceptable boundaries.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2004

Author dc:creator

• Granich Unikowsky, Adam, 1981-

Advisor dc:contributor.advisor

• Paul Stabler and Christopher J. Terman.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/28407

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/28407