Sieve : an XML-based structural Verilog rules check tool

The complexity of microprocessor chip designs continues to grow with every generation. At the same time, the amount of manpower needed for these projects also continues to grow, creating the need for a better integration flow. Due to this trend, many design conventions are set before the implementation of the chip commences to aid in the integration. This thesis describes the development of a suite of tools which check various design rules in accordance with predefined conventions, in particular the SCALE-0 VLSI design conventions. The tool suite consists of units that check naming conventions, units that check that the design is structural Verilog, and units that check leaf signal rules. A flexible input format for describing the rules is also developed so the tool can be easily adapted for new conventions and new chip designs. The input to the tools is a Verilog design file. Icarus Verilog is modified to parse this Verilog into an XML format. The tool then uses this format, along with the rules that have been defined, as inputs and performs the checks that are specified.

Department dc:contributor.department

Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science.

Grantor dc:publisher

Massachusetts Institute of Technology

Year dc:date.issued

2003

Author dc:creator

• Cheng, Tina, 1980-

Advisor dc:contributor.advisor

• Krste Asanović.

• Electrical Engineering and Computer Science.

Statement dc:rights

• M.I.T. theses are protected by copyright. They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. See provided URL for inquiries about permission.

Licence dc:rights.uri

• http://dspace.mit.edu/handle/1721.1/7582

Language dc:language.iso

en_US

Handle dc:identifier.uri

http://hdl.handle.net/1721.1/27091

OAI identifier oai:identifier

oai:dspace.mit.edu:1721.1/27091