Inquiry of Graphene Electronic Fabrication

<p>Graphene electronics represent a developing field where many material properties and devices characteristics are still unknown. Researching several possible fabrication processes creates a fabrication process using resources found at Cal Poly a local industry sponsor. The project attempts to produce a graphene network in the shape of a fractal Sierpinski carpet. The fractal geometry proves that PDMS microfluidic channels produce the fine feature dimensions desired during graphene oxide deposit. Thermal reduction then reduces the graphene oxide into a purified state of graphene. Issues arise during thermal reduction because of excessive oxygen content in the furnace. The excess oxygen results in devices burning and additional oxidation of the gate contacts that prevents good electrical contact to the gates. Zero bias testing shows that the graphene oxide resistance decreases after thermal reduction, proving that thermal reduction of the devices occurs. Testing confirms a fabrication process producing graphene electronics; however, revision of processing steps, especially thermal reduction, should greatly improve the yield and functionality of the devices.</p>

Name thesis:degree_name

MS in Electrical Engineering

Discipline thesis:degree_discipline

Electrical Engineering

Year dc:date.available

2016

Author dc:creator

• Greene, John Rausch

Contributors dc:contributor

• David Braun

• Graphene
• fabrication
• fractal
• microfluidics
• thermal reduction
• graphene oxide
• Electronic Devices and Semiconductor Manufacturing
• Semiconductor and Optical Materials

Identifier

10.15368/theses.2016.141

OAI identifier oai:identifier

oai:digitalcommons.calpoly.edu:theses-2840