Modellierung und Analyse arithmetikorientierter eFPGA-Architekturen

Digital signal processing systems typically consist of a data flow oriented and a control oriented part. Processors with reconfigurable accelerators are an attractive platform for implementing complex algorithms flexibly and at low physical implementation costs. The architecture of the accelerator has significant influence on the efficiency of the algorithms’ implementation. Several commercial and academic projects suggest that fine-grain reconfigurable FPGAs, so-called eFPGAs, are a well-suited architecture for this purpose. However, these projects typically focused on conventional FPGA architectures. In this thesis, an eFPGA architecture featuring a power- and area-efficiency significantly higher than conventional FPGAs is presented. The architecture is designed with respect to the typical requirements of arithmetic data paths, like high locality of the signal flow. To allow for a systematic analysis, the architecture is described as a general, parametrisable template. By carefully choosing the parameters, the efficiency of the eFPGA can be optimised for given arithmetic-oriented applications. Based on a generic description, three exemplary architecture alternatives implemented as physically optimised VLSI macros in 180nm- and 130nm-technologies are presented. The design methodology allows for passing certain architectural parameters to the hardware description of the macro. By means of an automatic design flow it is possible to analyse the influence of architecture parameters on the VLSI implementation with moderate effort. The implemented macros are used to analyse the potential for optimisation for arithmetic oriented eFPGAs quantitatively. For this, exemplary operators are implemented both on the eFPGAs and on commercially available FPGAs. Finally, a model based analysis of the conceived eFPGA architecture is presented in which the physical implementation costs of an eFPGA based on the aforementioned template are modelled as mathematic equations. This is achieved by implementing and characterising all key components like logic elements and configurable switches in a 90nm technology. By means of exemplary operations that are mapped to the eFPGA, the results are discussed regarding their subsumption in the design space, and the efficiency of the different architecture variants is evaluated. Based on the implementations and the model based results, a potential for optimisation with respect to power and area efficiency in mW/MOPS and MOPS/mm2 of up to one order of magnitude compared to commercial standard FPGAs is shown up.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2011

Author dc:creator

• Neumann, Bernd

Contributors dc:contributor

• Noll, Tobias G.

• info:eu-repo/classification/ddc/620
• Field programmable gate array
• Arithmetik
• VLSI
• Modellierung
• Ingenieurwissenschaften
• eFPGA
• arithmetic
• modelling

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

ger

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124474%22

OAI identifier oai:identifier

oai:publications.rwth-aachen.de:63003