Physical studies of strained Si/SiGe heterostructures : from virtual substrates to nanodevices

During the past two decades, the decrease in intrinsic delay of MOSFETs has been driven by the scaling of the device dimensions. The performance improvement has relied mostly in the increase of source velocity with gate scaling, while the transport properties of the channel have remained constant, i.e., those of conventional Si. Starting at the 90 nm node, uniaxial strain has been introduced in the transistor channel in order to further increase the source velocity. Beyond the 32 nm node, novel channel materials, with superior carrier velocities, and novel device architectures are required in order to continue the performance enhancement of MOSFETs while preserving the electrostatic control. In this Thesis, different physical aspects of strained Si and SiGe materials are investigated as a mean to increase carrier velocity in MOSFET channels. Novel approaches for the fabrication of strained Si based on ion implantation and anneal induced relaxation of virtual substrates are developed. The strain relaxation of SiGe layers is improved using a buried thin Si:C layer in the Si(100) substrate. Further, a Si+ ion implantation and annealing method is investigated for relaxing virtual substrates using lower implantation dose. Finally, the uniaxial relaxation of {110} surface oriented substrates is demonstrated using a He ion implantation and anneal technique. Apart of channel material studies, the fundamental and technological challenges involved in the integration of strained Si and SiGe into MOSFETs are assessed. The impact of source and drain formation on the elastic strain and electrical properties of strained Si layers and nanowires is examined. Also, the formation of ultra-shallow junction in strained Si/strained Si0:5Ge0:5/SSOI heterostructures is investigated using dierent types of ion implanted specie and annealing. The results show that BF+2 implantation and low temperature annealing are suitable approaches for achieving high quality, strained doped layers. The knowledge acquired was further applied in the fabrication of p-MOSFETs using strained Si/strained Si0:5Ge0:5/SSOI substrates and HfO2/TiN gate stacks. Moreover, rare earth GdScO3 was integrated for the first time into MOSFETs with high mobility strained SiGe channels using a gate-first process. Transistors with channel length ranging from 65 nm to 1.5 micm were fabricated and characterized. The hole mobility and effective velocity were extracted from devices with <110> and <100> channel orientations. The mobility for the <100> direction is 18% higher than for <110> direction. However, this enhancement translates in only 8% increase in effective velocity.

Grantor dc:publisher

Publikationsserver der RWTH Aachen University

Year dc:date

2011

Author dc:creator

• Minamisawa, Renato Amaral

Contributors dc:contributor

• Mantl, Siegfried

• info:eu-repo/classification/ddc/530
• Feldeffekttransistor
• Silicium
• Elastische Spannung
• Physik
• MOSFET
• nano
• Silicon
• Silicon Germanium
• Strain

Statement dc:rights

• info:eu-repo/semantics/openAccess

Language dc:language

eng

Identifier

https://publications.rwth-aachen.de/search?p=id:%22RWTH-CONV-124273%22

OAI identifier oai:identifier

oai:publications.rwth-aachen.de:62765